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[Submitted] cpu: Share the send functionality between traffic generators
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ahansson
|
December 6th, 2012, 7:59 p.m.
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[Submitted] base: Encapsulate the underlying fields in AddrRange
|
ahansson
|
October 30th, 2012, 8:57 a.m.
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[Submitted] mem: Tidy up bus addr range debug messages
|
ahansson
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November 1st, 2012, 1:49 a.m.
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[Submitted] mem: Skip address mapper range checks to allow more flexibility
|
ahansson
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December 6th, 2012, 8:02 p.m.
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[Submitted] config: Do not use hardcoded physmem in fs script
|
ahansson
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December 6th, 2012, 8:36 p.m.
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[Submitted] config: Traverse lists when visiting children in all proxy
|
ahansson
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December 6th, 2012, 8:08 p.m.
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[Submitted] mem: Add interleaving bits to the address ranges
|
ahansson
|
December 6th, 2012, 8:09 p.m.
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[Submitted] mem: Merge ranges that are part of the conf table
|
ahansson
|
December 6th, 2012, 8:16 p.m.
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[Submitted] dev: Make the ethernet devices use a non-zero clock
|
ahansson
|
December 6th, 2012, 8:18 p.m.
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[Submitted] sim: Fatal if a clocked object is set to have a clock of 0
|
ahansson
|
December 6th, 2012, 8:26 p.m.
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[Discarded] config: Do not use hardcoded physmem in fs script
|
ahansson
|
November 1st, 2012, 9:08 a.m.
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[Submitted] mem: Fix DRAM draining to ensure write queue is empty
|
ahansson
|
November 7th, 2012, 12:25 a.m.
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[Discarded] mem: Merge ranges that are part of the conf table
|
ahansson
|
November 1st, 2012, 10:38 a.m.
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[Submitted] config: Unify caches used in regressions and adjust L2 MSHRs
|
ahansson
|
October 26th, 2012, 9:55 a.m.
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[Submitted] config: Add a check for fastmem only used with Atomic CPU
|
ahansson
|
October 25th, 2012, 10:35 a.m.
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[Submitted] config: Remove unused mem_size in fs.py
|
ahansson
|
October 25th, 2012, 10:35 a.m.
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[Submitted] dev: Make default clock more reasonable for system and devices
|
ahansson
|
October 23rd, 2012, 2:28 a.m.
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[Submitted] config: Use SimpleDRAM in full-system, and with o3 and inorder
|
ahansson
|
October 20th, 2012, 8:44 a.m.
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[Submitted] arm: Use table walker clock that is inherited from CPU
|
ahansson
|
October 23rd, 2012, 2:25 a.m.
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[Submitted] config: Use shared cache config for regressions
|
ahansson
|
October 24th, 2012, 7:13 a.m.
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[Submitted] dev: Remove zero-time loop in DMA timing send
|
ahansson
|
October 19th, 2012, 2:29 a.m.
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[Submitted] Mem: Separate the host and guest views of memory backing store
|
ahansson
|
September 11th, 2012, 11:20 a.m.
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[Submitted] Checkpoint: Make system serialize call children
|
ahansson
|
October 12th, 2012, 1:46 a.m.
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[Submitted] Port: Add protocol-agnostic ports in the port hierarchy
|
ahansson
|
June 17th, 2012, 10:16 a.m.
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[Submitted] Mem: Use range operations in bus in preparation for striping
|
ahansson
|
September 21st, 2012, 9 a.m.
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[Submitted] Mem: Use deque instead of list for bus retries
|
ahansson
|
October 12th, 2012, 1:41 a.m.
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[Submitted] Fix: Address a few minor issues identified by cppcheck
|
ahansson
|
October 12th, 2012, 1:38 a.m.
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[Submitted] Param: Fix proxy traversal to support chained proxies
|
ahansson
|
September 21st, 2012, 9:05 a.m.
|
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[Submitted] Clock: Inherit the clock from parent by default
|
ahansson
|
September 21st, 2012, 9:06 a.m.
|
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[Submitted] Mem: Use cycles to express cache-related latencies
|
ahansson
|
September 28th, 2012, 7 a.m.
|
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[Submitted] Configs: Set the memtest clock to a reasonable value
|
ahansson
|
September 28th, 2012, 6:17 a.m.
|
|
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[Submitted] Regression: Use CPU clock and 32-byte width for L1-L2 bus
|
ahansson
|
September 27th, 2012, 6:30 a.m.
|
|
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[Submitted] Regression: Use addTwoLevelCacheHierarchy in configs
|
ahansson
|
September 27th, 2012, 6:28 a.m.
|
|
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[Submitted] Mem: Determine bus block size during initialisation
|
ahansson
|
September 21st, 2012, 9:03 a.m.
|
|
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[Submitted] Doxygen: Update the version of the Doxyfile
|
ahansson
|
September 28th, 2012, 9:56 a.m.
|
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[Submitted] Regression: Set the clock for twosys-tsunami CPUs
|
ahansson
|
September 21st, 2012, 9:54 a.m.
|
|
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[Submitted] TrafficGen: Add a basic traffic generator
|
ahansson
|
August 24th, 2012, 11:11 a.m.
|
|
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[Submitted] TrafficGen: Add a basic traffic generator regression
|
ahansson
|
August 24th, 2012, 11:20 a.m.
|
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[Submitted] DRAM: Introduce SimpleDRAM to capture a high-level controller
|
ahansson
|
September 10th, 2012, 10:30 a.m.
|
|
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[Submitted] Mem: Tidy up bus member variables types
|
ahansson
|
September 20th, 2012, 6:39 a.m.
|
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[Submitted] Scons: Verbose messages when dependencies are not installed
|
ahansson
|
September 20th, 2012, 6:22 a.m.
|
|
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[Submitted] AddrRange: Remove unused range_multimap
|
ahansson
|
September 3rd, 2012, 9:21 p.m.
|
|
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[Submitted] AddrRange: Simplify AddrRange params Python hierarchy
|
ahansson
|
August 29th, 2012, 11:52 a.m.
|
|
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[Submitted] AddrRange: Simplify Range by removing stream input/output
|
ahansson
|
September 3rd, 2012, 9:21 p.m.
|
|
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[Submitted] AddrRange: Transition from Range<T> to AddrRange
|
ahansson
|
September 3rd, 2012, 9:22 p.m.
|
|
|
|
[Submitted] Mem: Remove the file parameter from AbstractMemory
|
ahansson
|
September 10th, 2012, 9:15 a.m.
|
|
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|
[Submitted] Mem: Add a maximum bandwidth to SimpleMemory
|
ahansson
|
September 12th, 2012, 9:38 a.m.
|
|
|
|
[Submitted] gcc: Enable Link-Time Optimization for gcc >= 4.6
|
ahansson
|
May 2nd, 2012, 11:24 a.m.
|
|
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[Submitted] scons: Use c++0x with gcc >= 4.4 instead of 4.6
|
ahansson
|
September 13th, 2012, 3:22 a.m.
|
|
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[Submitted] scons: Add a target for google-perftools profiling
|
ahansson
|
September 10th, 2012, 9:53 a.m.
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