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[Submitted] cpu: Create record type enum for elastic traces
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cdunham
|
September 3rd, 2015, 4:17 p.m.
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[Submitted] cpu: Support virtual addr in elastic traces
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cdunham
|
September 3rd, 2015, 4:17 p.m.
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[Discarded] multi-gem5: Add an optional key parameter for the initparam pseudo instruction.
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cdunham
|
September 21st, 2015, 6:59 p.m.
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[Discarded] multi-gem5: Add support for config scripts to run parallel gem5 simulations
|
cdunham
|
September 21st, 2015, 6:59 p.m.
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[Discarded] multi-gem5: Fix draining and serialization
|
cdunham
|
September 21st, 2015, 6:59 p.m.
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[Discarded] multi-gem5: Fix packet ordering
|
cdunham
|
September 21st, 2015, 6:59 p.m.
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[Discarded] multi-gem5: Simplify checkpoint support
|
cdunham
|
September 21st, 2015, 6:59 p.m.
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[Submitted] base: support gzip-compressed object files
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cdunham
|
September 21st, 2015, 11:42 p.m.
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[Submitted] sim: Add ability to break at specific kernel function
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cdunham
|
September 30th, 2015, 9:42 p.m.
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[Submitted] sim: Add relative break scheduling
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cdunham
|
September 30th, 2015, 9:42 p.m.
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[Submitted] cpu: Enforce 1 interrupt controller per thread
|
cdunham
|
October 5th, 2015, 6:52 p.m.
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[Discarded] cpu: remove O3's fetch address validity check
|
cdunham
|
October 12th, 2015, 4:13 p.m.
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[Submitted] pseudo inst,util: Add an optional key parameter for the initparam pseudo instruction
|
cdunham
|
November 19th, 2015, 5:44 p.m.
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[Submitted] dist: Distributed Ethernet link support for distributed gem5 simulations
|
cdunham
|
November 19th, 2015, 5:44 p.m.
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[Submitted] dist: Config file and parameter changes for distributed gem5 simulations
|
cdunham
|
November 19th, 2015, 5:44 p.m.
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[Submitted] sim: always generate sim/tags.cc
|
cdunham
|
January 29th, 2016, 11:57 p.m.
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[Submitted] cpu: Fix LLSC atomic CPU wakeup
|
cdunham
|
February 9th, 2016, 9:29 p.m.
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[Submitted] arm: Squash after returning from exceptions in v7
|
cdunham
|
February 10th, 2016, 12:04 a.m.
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[Submitted] mem, cpu: Add assertions to snoop invalidation logic
|
cdunham
|
February 11th, 2016, 12:31 a.m.
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[Submitted] util: update Java JNI interface to m5ops
|
cdunham
|
February 13th, 2016, 12:33 a.m.
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[Submitted] cpu: Add SMT support to MinorCPU
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] cpu: Fix BTB threading oversight
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] mem: Remove threadId from memory request class
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] cpu: Add instruction opclass histogram to minor
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] cpu: Add an indirect branch target predictor
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] cpu: Implement per-thread GHRs
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] sim: Fix clock_domain unserialization
|
cdunham
|
February 25th, 2016, 11:56 p.m.
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[Submitted] sim: Add additional debug information when draining
|
cdunham
|
February 25th, 2016, 11:56 p.m.
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[Submitted] misc: Add secondary dot output for DVFS domains
|
cdunham
|
February 25th, 2016, 11:56 p.m.
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[Submitted] cpu: Query CPU for inst executed from Python
|
cdunham
|
March 4th, 2016, 11:03 p.m.
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[Submitted] sim: Adding thermal model support
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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[Submitted] sim: Thermal support for Linux
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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[Submitted] pwr: Low-power idle power state for idle CPUs
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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[Submitted] pwr: Add power states to ClockedObject
|
cdunham
|
March 5th, 2016, 12:21 a.m.
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[Submitted] sim: Adding support for power models
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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[Submitted] base: Add total() to Vector2D stat
|
cdunham
|
May 31st, 2016, 10:43 a.m.
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[Submitted] mem: Add snoop traffic statistic
|
cdunham
|
May 31st, 2016, 10:43 a.m.
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[Submitted] arm: invalidate TLB miscreg cache on modification of HSCTLR
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: change instruction classes to catch hyp traps
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: add stage2 translation support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: enable EL2 support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Add AArch64 hypervisor call instruction 'hvc'
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix EL perceived at TLB for address translation instructions
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Add check to fault routing for hypervisor/virtualization
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Refactor aarch64 table walk logic to remove redundancy
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix stage 2 determination in table walker
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix secure state checking in various places
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix trapping to Hypervisor during MSR/MRS read/write
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix stage 2 memory attribute checking in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Add TLBI instruction for stage 2 IPA's
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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