|
|
[Discarded] Changes to the gem5 memory-system (release-0.2)
|
ahansson
|
August 5th, 2011, 10:13 a.m.
|
|
|
|
[Discarded] MEM: FunctionalPorts are replaced with PortProxys
|
ahansson
|
November 28th, 2011, 10:22 a.m.
|
|
|
|
[Submitted] SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
|
ahansson
|
February 28th, 2012, 4:53 a.m.
|
|
|
|
[Submitted] MEM: Do not forward uncacheable to bus snoopers
|
ahansson
|
May 4th, 2012, 9:47 a.m.
|
|
|
|
[Submitted] Packet: Unify the use of PortID in packet and port
|
ahansson
|
May 23rd, 2012, 6:32 a.m.
|
|
|
|
[Submitted] Port: Add getAddrRanges to master port (asking slave port)
|
ahansson
|
June 6th, 2012, 9:44 a.m.
|
|
|
|
[Discarded] mem: Only forward the non-writable flag if truly needed
|
ahansson
|
December 9th, 2015, 11:58 p.m.
|
|
|
|
[Submitted] config: Use SimpleDRAM in full-system, and with o3 and inorder
|
ahansson
|
October 20th, 2012, 8:44 a.m.
|
|
|
|
[Submitted] mem: Add tTAW and tFAW to the SimpleDRAM model
|
ahansson
|
December 6th, 2012, 8:28 p.m.
|
|
|
|
[Submitted] mem: Cancel cache retry event when blocking port
|
ahansson
|
March 14th, 2013, 7:04 a.m.
|
|
|
|
[Submitted] cpu: Consider instructions waiting for FU completion in draining
|
ahansson
|
June 4th, 2013, 10:01 a.m.
|
|
|
|
[Submitted] dev: Include basic devices in NULL ISA build
|
ahansson
|
February 13th, 2014, 2:39 p.m.
|
|
|
|
[Submitted] mem: Make DRAM write queue draining more aggressive
|
ahansson
|
March 7th, 2014, 11:39 p.m.
|
|
|
|
[Submitted] scons: remove vector typemaps obsoleted by SWIG 2.0.4
|
ahansson
|
April 23rd, 2014, 12:11 p.m.
|
|
|
|
[Submitted] mem: Merge DRAM page-management calculations
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] style: Fixup strange semantics in hg m5style
|
ahansson
|
August 13th, 2014, 12:51 p.m.
|
|
|
|
[Submitted] cpu: Fix o3 quiesce fetch bug
|
ahansson
|
August 23rd, 2014, 5:08 a.m.
|
|
|
|
[Submitted] mem: Tie in the snoop filter in the coherent bus
|
ahansson
|
September 10th, 2014, 7:53 a.m.
|
|
|
|
[Submitted] scons: Generate a single debug flag C++ file
|
ahansson
|
September 29th, 2014, 10:37 a.m.
|
|
|
|
[Submitted] cpu: Move packet deallocation to recvTimingResp in the O3 CPU
|
ahansson
|
November 17th, 2014, 6:18 a.m.
|
|
|
|
[Submitted] mem: Support WriteInvalidate (again)
|
ahansson
|
November 25th, 2014, 9:49 a.m.
|
|
|
|
[Submitted] mem: Add a stack distance calculator
|
ahansson
|
December 12th, 2014, 5:45 p.m.
|
|
|
|
[Discarded] Changes to the gem5 memory-system (release-0.1)
|
ahansson
|
July 15th, 2011, 9:03 a.m.
|
|
|
|
[Submitted] arm, dev: Add a UFS device
|
ahansson
|
March 27th, 2015, 1:57 p.m.
|
|
|
|
[Submitted] clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
|
ahansson
|
April 2nd, 2012, 12:41 p.m.
|
|
|
|
[Submitted] ruby: Move Rubys cache class from Cache.py to RubyCache.py
|
ahansson
|
August 13th, 2015, 8:30 p.m.
|
|
|
|
[Submitted] mem: Enforce insertion order on the cache response path
|
ahansson
|
October 13th, 2015, 3:36 p.m.
|
|
|
|
[Submitted] Port: Align port names in C++ and Python
|
ahansson
|
June 11th, 2012, 7:46 a.m.
|
|
|
|
[Submitted] Clock: Move the clock and related functions to ClockedObject
|
ahansson
|
July 11th, 2012, 1:56 a.m.
|
|
|
|
[Submitted] AddrRange: Remove the unused range_ops header
|
ahansson
|
August 29th, 2012, 11:53 a.m.
|
|
|
|
[Submitted] Mem: Separate the host and guest views of memory backing store
|
ahansson
|
September 11th, 2012, 11:20 a.m.
|
|
|
|
[Submitted] Mem: Use cycles to express cache-related latencies
|
ahansson
|
September 28th, 2012, 7 a.m.
|
|
|
|
stats: Add example script to extract stats from SQL database
|
ahansson
|
January 15th, 2013, 10:27 a.m.
|
|
|
|
[Submitted] scons: Add warning for missing field initializers
|
ahansson
|
February 14th, 2013, 1:54 a.m.
|
|
|
|
[Submitted] mem: Adapt the LPDDR2 to match a single x32 channel
|
ahansson
|
April 22nd, 2013, 2:45 p.m.
|
|
|
|
[Submitted] cpu: add more instruction mix statistics
|
ahansson
|
April 23rd, 2014, 12:21 p.m.
|
|
|
|
[Submitted] cpu: Add ExecFlags debug flag
|
ahansson
|
September 10th, 2014, 7:51 a.m.
|
|
|
|
[Submitted] arch,x86,mem: Dynamically determine the ISA for Ruby store check
|
ahansson
|
September 29th, 2014, 10:39 a.m.
|
|
|
|
[Submitted] config: Add options to take/resume from SimPoint checkpoints
|
ahansson
|
November 20th, 2014, 9:43 a.m.
|
|
|
|
[Submitted] arch: Make readMiscRegNoEffect const throughout
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] tests: Run regression timeout as foreground
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] MEM: Remove the functional ports from the memory system
|
ahansson
|
December 19th, 2011, 6 a.m.
|
|
|
|
[Submitted] mem: Do not treat CleanEvict as a write operation
|
ahansson
|
October 30th, 2015, 10:33 a.m.
|
|
|
|
[Discarded] gcc: Enable tuning for native CPU features for gcc and clang
|
ahansson
|
July 2nd, 2012, 3:45 a.m.
|
|
|
|
[Submitted] DMA: Refactor the DMA device and align timing and atomic
|
ahansson
|
July 21st, 2012, 7:19 a.m.
|
|
|
|
[Submitted] mem: Fix cache sender state handling and add clarification
|
ahansson
|
December 9th, 2015, 11:51 p.m.
|
|
|
|
[Submitted] Mem: Use range operations in bus in preparation for striping
|
ahansson
|
September 21st, 2012, 9 a.m.
|
|
|
|
[Submitted] Mem: Use deque instead of list for bus retries
|
ahansson
|
October 12th, 2012, 1:41 a.m.
|
|
|
|
[Submitted] config: Traverse lists when visiting children in all proxy
|
ahansson
|
December 6th, 2012, 8:08 p.m.
|
|
|
|
[Submitted] mem: SimpleDRAM variable naming and whitespace fixes
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
