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[Submitted] X86: Generate code for 'm5_writefile'
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vilanova
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October 23rd, 2012, 11:27 a.m.
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[Submitted] Add command/pseudo-instruction m5fail
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vilanova
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October 23rd, 2012, 11:33 a.m.
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O3: Show per-stage aggregate statistics detailing the reasons for block/stall cycles
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vilanova
|
October 23rd, 2012, 11:38 a.m.
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[Submitted] config: Use shared cache config for regressions
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ahansson
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October 24th, 2012, 7:13 a.m.
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[Submitted] Ruby Config: Add Argument for marking caches as Inst Only - MESI/MOESI
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musleh
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October 24th, 2012, 8:18 a.m.
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[Submitted] ruby: support functional accesses in garnet flexible network
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nilay
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October 24th, 2012, 12:35 p.m.
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[Submitted] ruby: bug in functionalRead, revert recent changes
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nilay
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October 24th, 2012, 12:36 p.m.
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[Submitted] ruby: add functions for computing next stride/page address
|
nilay
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October 24th, 2012, 12:37 p.m.
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[Submitted] ruby: add a prefetcher
|
nilay
|
October 24th, 2012, 12:37 p.m.
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[Submitted] ruby: change slicc to allow for constructor args
|
nilay
|
October 24th, 2012, 12:38 p.m.
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[Submitted] ruby: modify the directed tester to read/write streams
|
nilay
|
October 24th, 2012, 12:39 p.m.
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[Submitted] ruby: add support for prefetching to MESI protocol
|
nilay
|
October 24th, 2012, 12:39 p.m.
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[Submitted] Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
|
ali
|
October 24th, 2012, 2:18 p.m.
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[Submitted] o3: Fix a couple of issues with the local predictor.
|
ali
|
October 24th, 2012, 2:18 p.m.
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[Submitted] sim: Fix as issue where exit events on instr queues are used after freed.
|
ali
|
October 24th, 2012, 2:19 p.m.
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[Submitted] ISA: generic Linux thread info support
|
ali
|
October 24th, 2012, 2:19 p.m.
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[Submitted] base: split out the VncServer into a VncInput and Server classes
|
ali
|
October 24th, 2012, 2:19 p.m.
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[Submitted] base: Fix a few incorrectly handled print format cases
|
ali
|
October 24th, 2012, 2:20 p.m.
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[Submitted] m5: Expose m5 pseudo-instructions to C/C++ via a static library
|
ali
|
October 24th, 2012, 2:21 p.m.
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[Submitted] base: Add missing header file to addr_range.hh.
|
ali
|
October 24th, 2012, 2:22 p.m.
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[Submitted] dev: Add missing inline declarations
|
ali
|
October 24th, 2012, 2:22 p.m.
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[Submitted] mips: Remove unused Python file
|
ali
|
October 24th, 2012, 2:23 p.m.
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[Submitted] pci: Make Python wrapper cast to the right type
|
ali
|
October 24th, 2012, 2:23 p.m.
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[Submitted] sim: Include object header files in SWIG interfaces
|
ali
|
October 24th, 2012, 2:26 p.m.
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[Submitted] dev: Fix ethernet device inheritance structure
|
ali
|
October 24th, 2012, 2:26 p.m.
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[Submitted] cpu: Add header files for checker CPUs
|
ali
|
October 24th, 2012, 2:27 p.m.
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[Submitted] cpu: O3 add a header declaring the DerivO3CPU
|
ali
|
October 24th, 2012, 2:28 p.m.
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[Submitted] sim: Move the draining interface into a separate base class
|
ali
|
October 24th, 2012, 2:32 p.m.
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[Submitted] sim: Reuse the code to change memory mode.
|
ali
|
October 24th, 2012, 2:33 p.m.
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[Submitted] python: Rename doDrain()->drain() and make it do the right thing
|
ali
|
October 24th, 2012, 2:52 p.m.
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[Submitted] sim: Add SWIG interface for Serializable
|
ali
|
October 24th, 2012, 3:03 p.m.
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[Submitted] arch: Make the ISA class inherit from SimObject
|
ali
|
October 24th, 2012, 3:04 p.m.
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[Submitted] ARM: Make ID registers ISA parameters
|
ali
|
October 24th, 2012, 3:05 p.m.
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[Submitted] sim: Add drain methods to request additional cleanup operations
|
ali
|
October 24th, 2012, 3:07 p.m.
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[Submitted] config: Remove unused mem_size in fs.py
|
ahansson
|
October 25th, 2012, 10:35 a.m.
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[Submitted] config: Add a check for fastmem only used with Atomic CPU
|
ahansson
|
October 25th, 2012, 10:35 a.m.
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[Submitted] ARM: dump stats and process info on context switches
|
ali
|
October 25th, 2012, 10:46 a.m.
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Ruby: MOESI Protocol Add missing AccessMode/prefetch Msg Fields
|
musleh
|
October 25th, 2012, 8:49 p.m.
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[Submitted] config: Unify caches used in regressions and adjust L2 MSHRs
|
ahansson
|
October 26th, 2012, 9:55 a.m.
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[Submitted] TournamentBP: Fix some bugs with table sizes and counters
|
erik.t
|
October 29th, 2012, 3:50 a.m.
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[Submitted] base: Encapsulate the underlying fields in AddrRange
|
ahansson
|
October 30th, 2012, 8:57 a.m.
|
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[Discarded] O3: Revert arm_detailed cache latencies
|
erik.t
|
October 31st, 2012, 5:05 a.m.
|
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[Submitted] InOrderCPU: Add Missing DPRINTF Argument to Fetch Unit
|
musleh
|
October 31st, 2012, 8:11 a.m.
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[Submitted] mem: Tidy up bus addr range debug messages
|
ahansson
|
November 1st, 2012, 1:49 a.m.
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[Discarded] config: Do not use hardcoded physmem in fs script
|
ahansson
|
November 1st, 2012, 9:08 a.m.
|
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[Discarded] mem: Merge ranges that are part of the conf table
|
ahansson
|
November 1st, 2012, 10:38 a.m.
|
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[Submitted] base: Create a central header listing all signals used within gem5
|
ali
|
November 2nd, 2012, 10:09 a.m.
|
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[Submitted] mem: Remove the IIC replacement policy
|
ali
|
November 2nd, 2012, 10:10 a.m.
|
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[Submitted] sim, arch: Add support for invalidating TLBs when draining
|
ali
|
November 2nd, 2012, 10:11 a.m.
|
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[Discarded] mem: Interface to allow HW-virtualized CPUs discover physical memory
|
ali
|
November 2nd, 2012, 10:12 a.m.
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