O3: Revert arm_detailed cache latencies
Review Request #1525 - Created Oct. 30, 2012 and discarded
| Information | |
|---|---|
| Erik Tomusk | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 9356:603d6ef97673 --------------------------- O3: Revert arm_detailed cache latencies Changeset 9322 changed the arm_detailed cache latencies from 1ns to 1 cycle. Since the default clock is 500ps, the latencies are now half of what they were. This patch doubles the latencies so they are identical to what they were before. This patch does NOT change the tol2bus clock back to 1GHz (currently 2GHz). Perhaps it should?
arm_detailed isn't covered by a regression. Confirmed that changes have expected effect on config.ini.
Posted (Oct. 30, 2012, 11:08 p.m.)
I would suggest you run with a 1 GHz clock instead. As you might have seen in the comments on the 1ns, that value was determined based on a 1GHz clock (and a 1 cycle latency). Thus, the current value is representative, and the problem is not the cache latency, but rather the clock. I hope that all makes sense.