cache: Allow main memory to be at disjoint address ranges.
Review Request #1087 - Created March 6, 2012 and submitted
| Information | |
|---|---|
| Ali Saidi | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 8881:249de1a823e6 --------------------------- cache: Allow main memory to be at disjoint address ranges.
Issue Summary
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| Description | From | Last Updated | Status |
|---|---|---|---|
| I'd suggest we use same expression as the iocache, i.e. call the parameter addr_ranges for both cache and bridge, and ... | Andreas Hansson | March 6, 2012, 4:40 p.m. | Open |
| 80 characters? | Andreas Hansson | March 6, 2012, 4:40 p.m. | Open |
| If we stick to how it is done in other places this could be simply AddrRange(mem_size) | Andreas Hansson | March 6, 2012, 4:40 p.m. | Open |
| How come this one is not using mem_size? Is it possible to rely on a parameter instead of a 256MB ... | Andreas Hansson | March 6, 2012, 4:40 p.m. | Open |
Posted (March 6, 2012, 4:40 p.m.)
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configs/example/fs.py (Diff revision 1) -
I'd suggest we use same expression as the iocache, i.e. call the parameter addr_ranges for both cache and bridge, and make the bridge [mem_size] as well in this case.
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src/mem/cache/BaseCache.py (Diff revision 1) -
80 characters?
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tests/configs/pc-o3-timing.py (Diff revision 1) -
If we stick to how it is done in other places this could be simply AddrRange(mem_size)
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tests/configs/realview-o3.py (Diff revision 1) -
How come this one is not using mem_size? Is it possible to rely on a parameter instead of a 256MB explicit string?