mem: Add DRAM cycle time

Information
Submitter:	Andreas Hansson
Repository:	gem5
Branch:	default
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Description

Changeset 10221:02b6fdd33908
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mem: Add DRAM cycle time

This patch extends the current timing parameters with the DRAM cycle
time. This is needed as the DRAMPower tool expects timestamps in DRAM
cycles. At the moment we could get away with doing this in a
post-processing step as the DRAMPower execution is separate from the
simulation run. However, in the long run we want the tool to be called
during the simulation, and then the cycle time is needed.

Testing Done

Why is the clock period associated with each clocked object not enough?

Andreas Hansson May 2, 2014, 12:16 a.m. (May 2, 2014, 12:16 a.m.)

There is a difference between the controller clock (which is what the DRAMCtrl clock domain would currently communicate), and the DRAM clock (tCK in DRAM speak). The other option compared to what we have done in this patch is to add a DRAM SimObject and let the DRAMCtrl have a pointer to it. The DRAM object could then be placed in a DRAM clock domain with tCK as its clock. That seems awfully bulky though.

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Status: Closed (submitted)