mem: add tCCD to DRAM controller
Review Request #2316 - Created July 23, 2014 and discarded
| Information | |
|---|---|
| Amin Farmahini | |
| gem5 | |
| Reviewers | |
| Default | |
This patch adds support for tCCD to the DRAM controller. After changeset 10211: e084db2b1527 (Merge DRAM latency calculation and bank state update), DRAM latency calculations has changed and that changeset provides a rather simple way to incorporate the tCCD parameter into latency calculations.
None
Posted (July 27, 2014, 5:34 p.m.)
Thanks for the input Amin. One high-level question: what is the main aim of the patch? Until now we have tried to keep the timing constraints to a minimum (without sacrificing fidelity). In general you could argue that tBURST can be used, rather than adding tCCD and then taking the max. Do you envision any use-cases where this is not the case?
