cpu: o3: Mapping the ZeroRegister for all hardware threads
Review Request #2851 - Created May 28, 2015 and updated
| Information | |
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| Alexandru Dutu | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10864:716172760d78 --------------------------- cpu: o3: Mapping the ZeroRegister for all hardware threads This patch helps enabling SMT in x86 by mapping the ZeroRegister to one physical register across all hardware threads.
Quick regressions passed for all ISAs.
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src/cpu/o3/cpu.cc (Diff revision 1) -
Wouldn't it be easier to just initialize the zero register index here using freeList.getIntReg() instead of doing it in the loop?
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src/cpu/o3/cpu.cc (Diff revision 1) -
If you initialize the zero register earlier, this would become:
const PhysRegIndex phys_reg = ridx != TheISA::ZeroReg ? freeList.getIntReg() : zero_phys_reg;
Looks functionally OK. Feel free to submit without another review round if you change the issue above.
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src/cpu/o3/cpu.cc (Diff revision 1) -
Initially, physical register are assigned consecutively to architectural register. We want to have just one physical register for all hardware threads. It seems that moving this outside the loop will accomplish the same behavior.
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src/cpu/o3/cpu.cc (Diff revision 1) -
This does not take care of different threads.
I'm happy with the explanation you just gave. Could you add that as a comment to clarify why the zero register is allocated in this way?
Change Summary:
Actually, giving this a second thought I like better the compressed version of this patch after Andreas's suggestion. Initially I was overly concerned with the unorderred initial mapping this will bring and the extra debugging confussion, however initial mappings change and there should not be much debugging on the register renaming front. So a compact code is the way to go.
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Diff: |
Revision 2 (+3 -1) |