A single HMC-2500 x32 model based on:

[1] DRAMSpec: a high-level DRAM bank modelling tool

developed at the University of Kaiserslautern. This high level tool

uses RC (resistance-capacitance) and CV (capacitance-voltage) models to

estimate the DRAM bank latency and power numbers.

[2] A Logic-base Interconnect for Supporting Near Memory Computation in the

Hybrid Memory Cube (E. Azarkhish et. al)

Assumed for the HMC model is a 30 nm technology node.

The modelled HMC consists of a 4 Gbit part with 4 layers connected with

TSVs. Each layer has 16 vaults and each vault consists of 2 banks per layer.

In order to be able to use the same controller used for 2D DRAM generations

for HMC, the following analogy is done:

Channel (DDR) => Vault (HMC)

device_size (DDR) => size of a single layer in a vault

ranks per channel (DDR) => number of layers

banks per rank (DDR) => banks per layer

devices per rank (DDR) => devices per layer ( 1 for HMC).

The parameters for which no input is available are inherited from the DDR3

configuration.

gem5 compiles. sweep.py runs