Curtis Dunham got review request #3000!
arm: Change TLB software caching
Review Request #3000 - Created July 30, 2015 and submitted - Latest diff uploaded
| Information | |
|---|---|
| Curtis Dunham | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
For the ARM ISA, certain variables are only updated when a necessary change is detected. Having 2 SMT threads share a TLB resulted in these not being updated as required. This patch adds a thread context identifer to assist in the invalidation of these variables.