Seems basically ok to me. It's a little odd to have mispredicts on non-control instructions, but that's how ARM does things I guess. Perhaps you could make the ISA description mark instructions changing R15 as control instructions? I'm sure that would be harder than it sounds.

src/cpu/o3/fetch_impl.hh (Diff revision 1)

I don't think there's actually a rule about it, but this || at the start of the line looks a little funny. I like them at the end of the line since that visually indicates the expression continues. Not a big deal, but it would be nice to move it.

src/cpu/o3/fetch_impl.hh (Diff revision 1)

I was really confused here for a second until I realized review board was ignoring the change in indentation.

src/cpu/o3/fetch_impl.hh (Diff revision 1)

Is it ever the case that branchMispredict is true but mispredictInst is not set?  I don't think so.  In that case I'd get rid of the redundant flag and clean up this control flow; I don't think nested ifs are needed (though I might be wrong).  Also the old comment doesn't really fit in context very well and should be updated.

src/cpu/o3/iew_impl.hh (Diff revision 1)

This line should be moved up to line 458 with the other misprediction-related signals.

src/cpu/o3/fetch_impl.hh (Diff revision 1)

hugely simplified:

        if (fromCommit->commitInfo[tid].branchMispredict &&
            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
                              fromCommit->commitInfo[tid].pc,
                              fromCommit->commitInfo[tid].branchTaken,
                              tid);
        } else {
            branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
                              tid);
        }