Add support for McVerSi memory consistency verification framework
Review Request #3449 - Created April 13, 2016 and updated - Latest diff uploaded
| Information | |
|---|---|
| Marco Elver | |
| gem5 | |
| default | |
| 3448 | |
| Reviewers | |
| Default | |
Add support for McVerSi memory consistency verification framework
This patch implements the Gem5-specific portion of McVerSi (a framework for simulation-based memory consistency verification) [1].
Architectures supported are:
- ARM (current mc2lib code generation only supports ARMv7).
- X86 (pseudo ops available via mmapped IPR interface).Currently, only the O3CPU is supported.
[1] http://ac.marcoelver.com/research/mcversi
Unless explicitly enabled (via loading appropriate workload), this component is unused.
Tested with ARM+Classic and X86+Ruby. Precompiled workloads that were used for testing available here: http://ac.marcoelver.com/res/mcversi_guest_workload_gem5.tar.gz
However, bugs have been found elsewhere in Gem5 while testing McVerSi (see http://www.mail-archive.com/gem5-dev@gem5.org/msg18940.html , and 1 of 2 bugs from paper http://reviews.gem5.org/r/2842/ ). (I will not restate them here to keep the discussion on topic.)