X86: Add L1 caches for the TLB walkers.
Review Request #454 - Created Jan. 29, 2011 and submitted
| Information | |
|---|---|
| Gabe Black | |
| gem5 | |
| Reviewers | |
| Default | |
| ali, gblack, nate, stever | |
X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.