Since there have been no objections, I'm going to commit this.

src/arch/x86/isa/insts/x87/control/save_x87_status_word.py (Diff revision 1)

Since FSTSW isn't an instruction it doesn't need to be mentioned.

src/arch/x86/isa/insts/x87/control/save_x87_status_word.py (Diff revision 1)

This information isn't useful here and shouldn't clutter the instruction definition.

src/arch/x86/isa/insts/x87/control/save_x87_status_word.py (Diff revision 1)

Reading the status register should automatically fold in the top register. If it doesn't it should. That shouldn't be implemented with microcode. Also, the string constants naming these registers can be set up in arch/x86/isa/microasm.isa by appending them to the "assembler.symbols" dict. Then they'll show up in the scope of the microcode and you can use "rdval t1, fsw"

With those changes, there's also no reason to construct the value in a temporary microcode register t1 in the AX case (FNSTSW_R).

src/arch/x86/isa/insts/x87/control/save_x87_status_word.py (Diff revision 1)

datasize will already be 2 because of the rAw operand. The w is interpreted as "word sized" which means datasize is set to 2 bytes. That's what I remember and what looking at the code seems to confirm, but it's been a while so let me know if you know that's not true.

src/arch/x86/isa/operands.isa (Diff revision 1)

This is never used and shouldn't be added.

src/arch/x86/regs/misc.hh (Diff revision 1)

This already exists as MISCREG_FSW. MISCREG_FCW is the control word, and MISCREG_FTW is the tag word.

I don't see any instructions in the simulator that update the x87 status register. Does it make sense to commit this code?