Review Board 2.0.15


CPU: Fix a case where timing simple cpu faults can nest.

Review Request #670 - Created May 2, 2011 and submitted

Information
Ali Saidi
gem5
Reviewers
Default
ali, gblack, nate, stever 
CPU: Fix a case where timing simple cpu faults can nest.

If we fault, change the state to faulting so that we don't fault again in the same cycle.

   

  


 


 

  

  









  
 


  

 
















 



 

  


 


  



   

   
Gabe Black

   
Posted  (May 3, 2011, 4:13 a.m.)


  


  


  

   
Could you please walk through when two faults will happen at the same time and why that's a problem?



  

   

   
    
    

   
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    mem op -> tlb miss -> delayed translation -> table walk -> fault -> fetch -> tlb miss -> table walk 

The table walker should never be called twice in one cycle. After the first fault we really want to unwind the call stack, let a cycle go by, and then start fetching handling the next instruction. 

These cases generate traces that are super hard to debug, unrealistic, and make debugging challenging so we should avoid them. 
    
    
    
   
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    Ah, ok. I think this is similar to that problem where the call stack wraps back around on itself too many times and tracedata gets deleted out from under an earlier frame by a later frame. It's good to break that cycle here, I think. I didn't see anything (other than my comment below) that was objectionable, so if you've tested it go ahead.
    
    
    
   
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          src/cpu/simple/timing.cc
          

           (Diff revision 1)

          
         
        

       
       
        
 


        
 


       
      

     

    

    


     
The reschedule function (with "always" set) will do the de/rescheduling for you all in one shot.




  

   

   
    
    

   
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    will fix. 
    
    
    
   
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