ARM: Further break up condition code into NZ, C, V bits.
Review Request #681 - Created May 4, 2011 and submitted
| Information | |
|---|---|
| Ali Saidi | |
| gem5 | |
| Reviewers | |
| Default | |
| ali, gblack, nate, stever | |
ARM: Further break up condition code into NZ, C, V bits. Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
Posted (May 8, 2011, 5:04 p.m.)
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src/arch/arm/faults.cc (Diff revision 1) -
The CPSR type has elements for some of these. You could add one for nz. That would eliminate the need for the shifts, and is a large part of what the bitunion types are for. Also be careful of order of operations.
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src/arch/arm/isa/formats/pred.isa (Diff revision 1) -
Watch order of operations. Even if it's technically correct, it's not immediately obvious. You might want to throw in parenthesis just to be clearer to a reader.
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src/arch/arm/isa/formats/pred.isa (Diff revision 1) -
It's not part of your change, but there should be a space around the :, I think.
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src/arch/arm/isa/insts/data.isa (Diff revision 1) -
Parenthesis, bitfields.
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src/arch/arm/isa/insts/fp.isa (Diff revision 1) -
Doesn't this change the behavior of this instruction? It used to write to a gpr, now it writes to the condition codes. Is that on purpose?
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src/arch/arm/isa/insts/ldr.isa (Diff revision 1) -
Parenthesis, bitfields.
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src/arch/arm/isa/insts/macromem.isa (Diff revision 1) -
Parenthesis, bitfields.
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src/arch/arm/isa/insts/macromem.isa (Diff revision 1) -
Bitfields.
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src/arch/arm/isa/insts/macromem.isa (Diff revision 1) -
Bitfields.
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src/arch/arm/isa/templates/pred.isa (Diff revision 1) -
Spaces after commas.
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src/arch/arm/nativetrace.cc (Diff revision 1) -
Why the shift up above but not here?
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src/arch/arm/utility.hh (Diff revision 1) -
The == 0x2 isn't needed since (nz & 0x2) will either be 0x2 or 0. That maps to true and false naturally.
Posted (May 9, 2011, 12:02 a.m.)
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src/arch/arm/faults.cc (Diff revision 1) -
will switch to the bit fields.
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src/arch/arm/isa/formats/pred.isa (Diff revision 1) -
ok
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src/arch/arm/isa/insts/data.isa (Diff revision 1) -
yup
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src/arch/arm/isa/insts/fp.isa (Diff revision 1) -
It used to write IntRegCondCodes, it just did it with the cond code register being passed in to the constructor instead of just using CondCodes.
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src/arch/arm/isa/insts/ldr.isa (Diff revision 1) -
yup
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src/arch/arm/isa/insts/macromem.isa (Diff revision 1) -
yup
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src/arch/arm/isa/insts/macromem.isa (Diff revision 1) -
yup
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src/arch/arm/isa/insts/macromem.isa (Diff revision 1) -
yup
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src/arch/arm/isa/templates/pred.isa (Diff revision 1) -
yup
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src/arch/arm/nativetrace.cc (Diff revision 1) -
yup
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src/arch/arm/utility.hh (Diff revision 1) -
ok