Review Board 2.0.15


LSQ: Fix a few issues with the storeset predictor.

Review Request #793 - Created July 15, 2011 and submitted

Information
Ali Saidi
gem5
Reviewers
Default
ali, gblack, nate, stever
LSQ: Fix a few issues with the storeset predictor.

Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
   the barrier was squashed instead of committed. This made all load insts
   dependent on a non-existent barrier in-flight.

   
Posted (July 24, 2011, 5:34 p.m.)
I ran the X86 regressions with these patches and my uncommitted X86_FS patches, and other than some expected stat differences everything seems ok. It looks like the bulk of this patch is actually changes to the DPRINTFs. That should go in a separate patch since it isn't integral to what this one is trying to do. It should be trivial to separate out and they can be submitted next to each other. Minor style nits are noted.
src/cpu/o3/mem_dep_unit_impl.hh (Diff revision 1)
 
 
space after the comma
src/cpu/o3/mem_dep_unit_impl.hh (Diff revision 1)
 
 
space between if and ( here and below