Review Board 2.0.15


ARM: Add support for having a TLB cache.

Review Request #904 - Created Nov. 3, 2011 and submitted

Information
Ali Saidi
gem5
Reviewers
Default
ali, gblack, nate, stever
ARM: Add support for having a TLB cache.

   
Posted (Nov. 5, 2011, 6:15 p.m.)



  
src/cpu/BaseCPU.py (Diff revision 1)
 
 
This is wrong. Boiled down, it's saying:

if x86 or arm:
    foo;
elif x86 or arm:
    bar;

bar will never happen. It's not quite that simple, but that doesn't change the nature of the problem. Have you run regressions on this? I expect it will cause problems in at least one of x86 or ARM.
  1. No it's saying in x86 or arm and there is a tlb cache specified, then do foo, otherwise if you didn't select a tlb cache in your config do  bar
Posted (Nov. 8, 2011, 3:17 a.m.)



  
src/cpu/BaseCPU.py (Diff revision 1)
 
 
Wouldn't it be equivalent to write:

if buildEnv['FULL_SYSTEM'] and buildEnv['TARGET_ISA'] in ['x86', 'arm']:
    if iwc and dwc:
        [stuff]
    else:
        [other stuff]

??

Assuming I haven't missed some corner case, this sure seems clearer to me.
  1. Sure... that is fine.
  2. Yes, I agree. I think I see why it's not actually wrong, but now we have experimental proof that it's a bit confusing.
Posted (Nov. 17, 2011, 6:21 p.m.)



  
src/cpu/BaseCPU.py (Diff revision 1)
 
 
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