|
|
[Submitted] ext: disable PLY debugging
|
ahansson
|
April 23rd, 2014, 12:11 p.m.
|
|
|
|
[Submitted] mem: Add tWR to DRAM activate and precharge constraints
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] arm: use condition code registers for ARM ISA
|
ahansson
|
August 13th, 2014, 2:07 p.m.
|
|
|
|
[Submitted] x86: Flag instructions that call suspend as IsQuiesce
|
ahansson
|
August 28th, 2014, 7:31 a.m.
|
|
|
|
[Submitted] arm: Add a model of an ARM PMUv3
|
ahansson
|
September 29th, 2014, 10:38 a.m.
|
|
|
|
[Submitted] scons: Avoid implicit command dependencies
|
ahansson
|
November 30th, 2014, 9:39 a.m.
|
|
|
|
[Submitted] mem: Fix bug relating to writebacks and prefetches
|
ahansson
|
December 12th, 2014, 5:49 p.m.
|
|
|
|
[Submitted] mem: Clarify cache behaviour for pending dirty responses
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
|
|
|
[Submitted] config: Add soak test for memtest.py
|
ahansson
|
March 6th, 2015, 1:39 p.m.
|
|
|
|
[Submitted] arch, cpu: Do not forward snoops to table walker
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
|
|
[Submitted] SWIG: Make gem5 compile and link with swig 2.0.4
|
ahansson
|
December 19th, 2011, 5:51 a.m.
|
|
|
|
[Submitted] MEM: Prepare mport for master/slave split
|
ahansson
|
February 20th, 2012, 2:55 a.m.
|
|
|
|
[Submitted] mem: Add explicit Cache subclass and make BaseCache abstract
|
ahansson
|
August 13th, 2015, 8:31 p.m.
|
|
|
|
[Submitted] mem: Enforce insertion order on the cache response path
|
ahansson
|
October 13th, 2015, 3:36 p.m.
|
|
|
|
[Submitted] base: Add wrapped protobuf input stream
|
ahansson
|
December 6th, 2012, 7:53 p.m.
|
|
|
|
stats: Add length of all stats to the SQL stats table
|
ahansson
|
January 15th, 2013, 10:33 a.m.
|
|
|
|
[Submitted] mem: More descriptive enum names for address mapping
|
ahansson
|
March 28th, 2013, 3:28 a.m.
|
|
|
|
[Submitted] cpu: Block traffic generator when requests have to retry
|
ahansson
|
April 23rd, 2013, 12:29 a.m.
|
|
|
|
[Submitted] mem: Remove the cache builder
|
ahansson
|
May 23rd, 2013, 12:44 a.m.
|
|
|
|
[Discarded] scons: Move the warning about self assignment to SWIG code only
|
ahansson
|
June 28th, 2013, 10:34 a.m.
|
|
|
|
[Submitted] alpha: Move system virtProxy to Alpha only
|
ahansson
|
August 19th, 2013, 9:34 a.m.
|
|
|
|
[Submitted] mem: Use the same timing calculation for DRAM read and write
|
ahansson
|
October 16th, 2013, 7:40 a.m.
|
|
|
|
[Submitted] arch, arm: Preserve TLB bootUncacheability when switching CPUs
|
ahansson
|
April 23rd, 2014, 12:22 p.m.
|
|
|
|
[Submitted] scons: Warn for incompatible gcc and binutils
|
ahansson
|
July 28th, 2014, 5:50 a.m.
|
|
|
|
[Submitted] dev: Add a VirtIO console device model
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] arch: Use shared_ptr for all Faults
|
ahansson
|
September 29th, 2014, 10:40 a.m.
|
|
|
|
[Submitted] mem: Add a GDDR5 DRAM config
|
ahansson
|
November 17th, 2014, 6:13 a.m.
|
|
|
|
[Submitted] x86: Delay X86 table walk on receiving walker response
|
ahansson
|
January 5th, 2015, 4:35 p.m.
|
|
|
|
[Submitted] arm: Wire up the GIC with the platform in the base class
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
|
|
[Submitted] mem: Add byte mask to Packet::checkFunctional
|
ahansson
|
February 19th, 2015, 7:56 a.m.
|
|
|
|
[Submitted] mem: Remove redundant allocateUncachedReadBuffer in cache
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
|
|
[Submitted] Atomic: Remove the physmem_port and access memory directly
|
ahansson
|
March 20th, 2012, 10:30 a.m.
|
|
|
|
[Submitted] MEM: Use base class Master/SlavePort pointers in the bus
|
ahansson
|
April 9th, 2012, 9:40 a.m.
|
|
|
|
[Submitted] mem: Make the coherent crossbar account for timing snoops
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] mem: Do not treat CleanEvict as a write operation
|
ahansson
|
October 30th, 2015, 10:33 a.m.
|
|
|
|
[Submitted] arm: Use table walker clock that is inherited from CPU
|
ahansson
|
October 23rd, 2012, 2:25 a.m.
|
|
|
|
[Submitted] mem: Add DDR3 and LPDDR2 DRAM controller configurations
|
ahansson
|
December 6th, 2012, 8:31 p.m.
|
|
|
|
[Submitted] config: Break out base options for usage with NULL ISA
|
ahansson
|
October 20th, 2016, 11:07 a.m.
|
|
|
|
[Submitted] mem: Fix CommMonitor style and response check
|
ahansson
|
June 4th, 2013, 10:47 a.m.
|
|
|
|
[Submitted] cpu: Fix TrafficGen trace playback
|
ahansson
|
July 18th, 2013, 1:17 p.m.
|
|
|
|
[Submitted] mem: Wakeup sleeping CPUs without caches on LLSC
|
ahansson
|
February 21st, 2014, 1:21 p.m.
|
|
|
|
[Submitted] mem: Limit the accesses to a page before forcing a precharge
|
ahansson
|
March 7th, 2014, 11:40 p.m.
|
|
|
|
[Submitted] scons: Bump the compiler version to gcc 4.6 and clang 3.0
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
|
|
|
|
[Submitted] arm: allow DC instructions by default so SE mode works
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
|
|
|
|
[Submitted] style: Fixup strange semantics in hg m5style
|
ahansson
|
August 13th, 2014, 12:51 p.m.
|
|
|
|
[Submitted] cpu: Fix o3 quiesce fetch bug
|
ahansson
|
August 23rd, 2014, 5:08 a.m.
|
|
|
|
[Submitted] mem: Tie in the snoop filter in the coherent bus
|
ahansson
|
September 10th, 2014, 7:53 a.m.
|
|
|
|
[Submitted] scons: Add --without-tcmalloc build option
|
ahansson
|
September 29th, 2014, 10:37 a.m.
|
|
|
|
[Submitted] cpu, o3: Ignored invalidate causing same-address load reordering
|
ahansson
|
November 17th, 2014, 6:18 a.m.
|
|
|
|
[Submitted] mem: Add rank-wise refresh to the DRAM controller
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
