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[Submitted] MEM: Remove the Broadcast destination from the packet
|
ahansson
|
April 4th, 2012, 12:52 a.m.
|
|
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[Submitted] mem: Remove templates in cache model
|
ahansson
|
March 30th, 2015, 9:16 a.m.
|
|
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[Discarded] mem: Remove RubyMemoryControl and rely on DRAMCtrl
|
ahansson
|
April 2nd, 2015, 9:31 a.m.
|
|
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|
[Submitted] mem: Remove redundant Packet::allocate calls
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
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[Submitted] mem: Remove redundant is_top_level cache parameter
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
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[Submitted] mem: Remove redundant allocateUncachedReadBuffer in cache
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
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[Submitted] mem: Remove printing of DRAM params
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
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[Submitted] MEM: Remove Port removeConn and MemObject deletePortRefs
|
ahansson
|
December 19th, 2011, 5:57 a.m.
|
|
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[Submitted] mem: Remove Packet source from ForwardResponseRecord
|
ahansson
|
January 12th, 2015, 4:09 p.m.
|
|
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[Submitted] MEM: Remove onRetryList from BusPort and rely on retryList
|
ahansson
|
January 18th, 2012, 2:29 a.m.
|
|
|
|
[Submitted] mem: Remove null-check bypassing in Packet::getPtr
|
ahansson
|
November 17th, 2014, 6:13 a.m.
|
|
|
|
[Submitted] MEM: Remove legacy DRAM in preparation for memory updates
|
ahansson
|
March 21st, 2012, 10:04 a.m.
|
|
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|
[Submitted] mem: Remove extraneous acquire/release flags and attributes
|
ahansson
|
August 5th, 2015, 8:51 a.m.
|
|
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|
[Submitted] mem: Remove DRAMSim2 DDR3 configuration
|
ahansson
|
September 29th, 2014, 10:41 a.m.
|
|
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|
[Submitted] mem: Relax packet src/dest check and shift onus to crossbar
|
ahansson
|
November 17th, 2014, 6:17 a.m.
|
|
|
|
mem: Reflect that packet address and size are always valid
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] mem: Refactor assignment of Packet types
|
ahansson
|
August 13th, 2014, 2:07 p.m.
|
|
|
|
[Submitted] MEM: Prepare mport for master/slave split
|
ahansson
|
February 20th, 2012, 2:55 a.m.
|
|
|
|
[Submitted] mem: Pick the next DRAM request based on bank availability
|
ahansson
|
October 16th, 2013, 7:41 a.m.
|
|
|
|
[Submitted] mem: Perform write merging in the DRAM write queue
|
ahansson
|
August 5th, 2013, 4:55 p.m.
|
|
|
|
[Submitted] MEM: Pass the ports from Python to C++ using the Swig params
|
ahansson
|
January 18th, 2012, 2:32 a.m.
|
|
|
|
[Submitted] mem: Pass shared downstream through caches
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
|
|
[Submitted] mem: Order packet queue only on matching addresses
|
ahansson
|
October 13th, 2015, 3:36 p.m.
|
|
|
|
[Submitted] mem: Only track snooping ports in the snoop filter
|
ahansson
|
August 21st, 2015, 3:50 p.m.
|
|
|
|
[Discarded] mem: Only forward the non-writable flag if truly needed
|
ahansson
|
December 9th, 2015, 11:58 p.m.
|
|
|
|
[Submitted] mem: Move the point of coherency to the coherent crossbar
|
ahansson
|
January 1st, 2016, 2:33 p.m.
|
|
|
|
[Submitted] MEM: Move port creation to the memory object(s) construction
|
ahansson
|
February 14th, 2012, 10:39 a.m.
|
|
|
|
[Submitted] mem: Move crossbar default latencies to subclasses
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] mem: Move cache_impl.hh to cache.cc
|
ahansson
|
August 13th, 2015, 8:29 p.m.
|
|
|
|
[Submitted] MEM: Move all read/write blob functions from Port to PortProxy
|
ahansson
|
February 15th, 2012, 5:58 a.m.
|
|
|
|
[Submitted] mem: More descriptive enum names for address mapping
|
ahansson
|
March 28th, 2013, 3:28 a.m.
|
|
|
|
[Submitted] mem: More descriptive DRAM config names
|
ahansson
|
May 14th, 2013, 12:45 a.m.
|
|
|
|
[Submitted] mem: More descriptive address-mapping scheme names
|
ahansson
|
March 7th, 2014, 11:35 p.m.
|
|
|
|
[Discarded] mem: Modernise the CacheSet class, and avoid templates
|
ahansson
|
August 31st, 2015, 9:20 a.m.
|
|
|
|
[Submitted] mem: Modernise MSHR iterators to C++11
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
|
|
[Submitted] mem: mmap the backing store with MAP_NORESERVE
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Discarded] mem: Merge ranges that are part of the conf table
|
ahansson
|
November 1st, 2012, 10:38 a.m.
|
|
|
|
[Submitted] mem: Merge ranges that are part of the conf table
|
ahansson
|
December 6th, 2012, 8:16 p.m.
|
|
|
|
[Submitted] mem: Merge ranges in bus before passing them on
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Merge interleaved ranges when creating backing store
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Merge DRAM page-management calculations
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Merge DRAM latency calculation and bank state update
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Make tXAW enforcement less conservative and per rank
|
ahansson
|
October 16th, 2013, 7:42 a.m.
|
|
|
|
[Submitted] mem: Make the XBar responsible for tracking response routing
|
ahansson
|
January 5th, 2015, 4:36 p.m.
|
|
|
|
[Submitted] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
|
ahansson
|
January 18th, 2012, 2:35 a.m.
|
|
|
|
[Submitted] mem: Make the requests carried by packets const
|
ahansson
|
November 17th, 2014, 6:15 a.m.
|
|
|
|
[Submitted] mem: Make the coherent crossbar account for timing snoops
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] mem: Make the buses multi layered
|
ahansson
|
April 22nd, 2013, 3:35 p.m.
|
|
|
|
[Submitted] MEM: Make the bus default port yet another port
|
ahansson
|
December 23rd, 2011, 1:38 a.m.
|
|
|
|
[Submitted] MEM: Make the bus bridge unidirectional and fixed address range
|
ahansson
|
December 23rd, 2011, 1:32 a.m.
|
|
