|
|
[Submitted] mem: Remove threadId from memory request class
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
|
|
|
[Submitted] cpu: Add instruction opclass histogram to minor
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
|
|
|
[Submitted] cpu: Add an indirect branch target predictor
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
|
|
|
[Submitted] cpu: Implement per-thread GHRs
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
|
|
|
[Submitted] sim: Fix clock_domain unserialization
|
cdunham
|
February 25th, 2016, 11:56 p.m.
|
|
|
|
[Submitted] sim: Add additional debug information when draining
|
cdunham
|
February 25th, 2016, 11:56 p.m.
|
|
|
|
[Submitted] misc: Add secondary dot output for DVFS domains
|
cdunham
|
February 25th, 2016, 11:56 p.m.
|
|
|
|
[Submitted] cpu: Query CPU for inst executed from Python
|
cdunham
|
March 4th, 2016, 11:03 p.m.
|
|
|
|
[Submitted] sim: Adding thermal model support
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
|
|
|
[Submitted] sim: Thermal support for Linux
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
|
|
|
[Submitted] pwr: Add power states to ClockedObject
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
|
|
|
[Submitted] pwr: Low-power idle power state for idle CPUs
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
|
|
|
[Submitted] sim: Adding support for power models
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
|
|
|
[Submitted] base: Add total() to Vector2D stat
|
cdunham
|
May 31st, 2016, 10:43 a.m.
|
|
|
|
[Submitted] mem: Add snoop traffic statistic
|
cdunham
|
May 31st, 2016, 10:43 a.m.
|
|
|
|
[Submitted] arm: invalidate TLB miscreg cache on modification of HSCTLR
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: change instruction classes to catch hyp traps
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: add stage2 translation support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: enable EL2 support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Add AArch64 hypervisor call instruction 'hvc'
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Fix EL perceived at TLB for address translation instructions
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Add check to fault routing for hypervisor/virtualization
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Refactor aarch64 table walk logic to remove redundancy
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Fix stage 2 determination in table walker
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Fix secure state checking in various places
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Fix trapping to Hypervisor during MSR/MRS read/write
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Fix stage 2 memory attribute checking in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Add TLBI instruction for stage 2 IPA's
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: correctly assign faulting IPA's to HPFAR_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: Check TLB stage 2 permissions in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: warn not fail on use of missing miscreg CNTHCTL_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] arm: refactor page table walking
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Submitted] isa: Modify get/check interrupt routines
|
cdunham
|
July 5th, 2016, 2 p.m.
|
|
|
|
[Submitted] cpu: Fix Minor SMT WFI/drain interaction issues
|
cdunham
|
July 5th, 2016, 2 p.m.
|
|
|
|
[Submitted] arm, config: Add an example ARM big.LITTLE(tm) configuration script
|
cdunham
|
July 8th, 2016, 10:28 a.m.
|
|
|
|
[Submitted] arm: bank GIC registers per CPU
|
cdunham
|
July 18th, 2016, 3:26 p.m.
|
|
|
|
[Submitted] arm: s/ctx_id/ctx/ the GIC
|
cdunham
|
July 18th, 2016, 3:26 p.m.
|
|
|
|
[Submitted] mem: make DDR4 x16
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: add DRAM powerdown timing
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: update DDR3 die revision
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: Sort memory commands and update DRAMPower
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: Modify drain to ensure banks and power are idled
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: Add callback to compute stats prior to dump event
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: Add DRAM low-power functionality
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: add DRAM powerdown current
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] isa,arm: Add missing AArch32 FP instructions
|
cdunham
|
August 16th, 2016, 1:31 p.m.
|
|
|
|
[Discarded] arm, config: Fixups for the example big.LITTLE(tm) configuration
|
cdunham
|
August 16th, 2016, 1:56 p.m.
|
|
|
|
cpu: Add a SynchroTrace replay model
|
cdunham
|
October 26th, 2016, 11:04 p.m.
|
|
|
|
[Submitted] dist, dev: fix etherswitch upgrade script
|
cdunham
|
December 15th, 2016, 4:50 p.m.
|
|
|
|
[Submitted] sim: add support for checkpoint downgrading
|
cdunham
|
December 15th, 2016, 4:51 p.m.
|
|
