Review Board 2.0.15


Review requests for Default

Summary Submitter
Posted Last Updated
mem: Add optional request flags to the packet trace
ahansson
March 14th, 2013, 7 a.m.
mem: Add basic stats to the buses
ahansson
April 5th, 2013, 6:39 a.m.
cpu: Prune the stale TraceCPU
ahansson
April 27th, 2013, 12:17 p.m.
mem: Allow disabling of tXAW through a 0 activation limit
ahansson
July 12th, 2013, 9:46 a.m.
arch: Resurrect the NOISA build target and rename it NULL
ahansson
August 19th, 2013, 9:42 a.m.
mem: Just-in-time write scheduling in DRAM controller
ahansson
October 16th, 2013, 7:45 a.m.
mem: Filter cache snoops based on address ranges
ahansson
January 23rd, 2014, 8:23 a.m.
cpu: Make CPU and ThreadContext getters const
ahansson
March 6th, 2014, 7:22 p.m.
sim, arm: implement more of the at variety syscalls
ahansson
April 23rd, 2014, 12:26 p.m.
sim: bump checkpoint version for multiple event queues
ahansson
August 13th, 2014, 12:49 p.m.
config: Add port splicing capability to PortRef class
ahansson
August 20th, 2014, 8:35 a.m.
energy: Memory-mapped Energy Controller component
ahansson
September 10th, 2014, 7:53 a.m.
mem: DRAMPower integration for on-line DRAM power stats
ahansson
September 29th, 2014, 10:44 a.m.
mem: Add checks and explanation for assertMemInhibit usage
ahansson
November 17th, 2014, 6:14 a.m.
arm: Add support for filtering in the PMU
ahansson
December 12th, 2014, 5:44 p.m.
mem: Remove Packet source from ForwardResponseRecord
ahansson
January 12th, 2015, 4:09 p.m.
mem: Clarification of packet crossbar timings
ahansson
February 5th, 2015, 12:52 p.m.
cpu: Fix a bug in counting issued instructions in MinorCPU
ahansson
May 8th, 2015, 1:11 p.m.
mem: Remove redundant is_top_level cache parameter
ahansson
June 10th, 2015, 7:59 a.m.
MEM: Remove onRetryList from BusPort and rely on retryList
ahansson
January 18th, 2012, 2:29 a.m.
mem: Convert Request static const flags to enums
ahansson
June 26th, 2015, 9:26 p.m.
MEM: Fatal when no port can be found for an address
ahansson
February 12th, 2012, 10:22 a.m.
mem: Tidy up CacheBlk class
ahansson
July 13th, 2015, 3:15 p.m.
CPU: Check that the interrupt controller is created when needed
ahansson
March 2nd, 2012, 4:45 a.m.
MEM: Enable multiple distributed generalized memories
ahansson
March 21st, 2012, 4:20 p.m.
Bus: Split the bus into a non-coherent and coherent bus
ahansson
May 25th, 2012, 9:47 a.m.
Power: Fix MaxMiscDestRegs which was set to zero
ahansson
June 8th, 2012, 2:54 a.m.
Fix: Address a few benign memory leaks
ahansson
July 6th, 2012, 12:18 a.m.
mem: Do not rely on the NeedsWritable flag for responses
ahansson
December 29th, 2015, 4:16 p.m.
Checker: Bump the realview-o3-checker regression
ahansson
August 25th, 2012, 4 a.m.
Mem: Remove the file parameter from AbstractMemory
ahansson
September 10th, 2012, 9:15 a.m.
configs: Add a lat_mem_rd style test script
ahansson
February 15th, 2016, 9:01 a.m.
mem: Add deferred packet class to prefetcher
ahansson
February 14th, 2013, 1:52 a.m.
mem: Add static latency to the DRAM controller
ahansson
May 11th, 2013, 10:28 a.m.
config: Add a BaseSESystem builder for re-use in regressions
ahansson
June 6th, 2013, 2:30 p.m.
config: Remove Clock parameter multiplication
ahansson
June 11th, 2013, 9:31 a.m.
dev: Set HDLCD default pixel clock for 1080p @ 60Hz
ahansson
April 23rd, 2014, 12:18 p.m.
mem: Add DRAM cycle time
ahansson
April 23rd, 2014, 12:37 p.m.
arm: Fix v8 neon latency issue for loads/stores
ahansson
August 13th, 2014, 2:07 p.m.
cpu: Remove unused deallocateContext calls
ahansson
September 11th, 2014, 2:01 p.m.
arm: Add a model of an ARM PMUv3
ahansson
September 29th, 2014, 10:38 a.m.
mem: Rework the structuring of the prefetchers
ahansson
December 12th, 2014, 5:47 p.m.
style: Update the style checker to handle new include order
ahansson
January 26th, 2015, 5:55 p.m.
arm: Add a GICv2m device
ahansson
March 6th, 2015, 1:39 p.m.
mem: Pass shared downstream through caches
ahansson
March 30th, 2015, 9:17 a.m.
MEM: Add port proxies instead of non-structural ports
ahansson
December 19th, 2011, 5:53 a.m.
MEM: Differentiate functional cache accesses from CPU and memory
ahansson
January 5th, 2012, 5:17 a.m.
Ruby: Connect system port in Ruby network test
ahansson
January 27th, 2012, 3:57 a.m.
mem: Do not include snoop-filter latency in crossbar occupancy
ahansson
August 19th, 2015, 9:06 a.m.
swig: Use SWIG from environment when determining version
ahansson
June 20th, 2012, 4:32 p.m.
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