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[Submitted] arm: Clean up and document decoder API
|
ahansson
|
December 12th, 2014, 5:45 p.m.
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[Submitted] mem: Remove unused Packet src and dest fields
|
ahansson
|
January 12th, 2015, 4:10 p.m.
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[Submitted] mem: Fix cache MSHR conflict determination
|
ahansson
|
February 23rd, 2015, 1:05 p.m.
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[Submitted] mem: Allocate cache writebacks before new MSHRs
|
ahansson
|
March 22nd, 2015, 7:35 a.m.
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[Submitted] mem: Delay responses in the crossbar before forwarding
|
ahansson
|
June 15th, 2015, 6:06 p.m.
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[Submitted] MEM: Introduce the master/slave port roles in the Python classes
|
ahansson
|
January 18th, 2012, 2:31 a.m.
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[Submitted] mem: Transition away from isSupplyExclusive for writebacks
|
ahansson
|
July 13th, 2015, 3:16 p.m.
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[Submitted] Ruby: Rename RubyPort::sendTiming to avoid overriding base class
|
ahansson
|
March 2nd, 2012, 5:55 a.m.
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[Submitted] misc: Remove redundant compiler-specific defines
|
ahansson
|
October 8th, 2015, 2:29 p.m.
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[Submitted] Bus: Replace tickNextIdle and inRetry with a state variable
|
ahansson
|
June 8th, 2012, 10:54 a.m.
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[Submitted] Port: Hide the queue implementation in SimpleTimingPort
|
ahansson
|
July 6th, 2012, 6:31 a.m.
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[Submitted] Clock: Add a Cycles wrapper class and use where applicable
|
ahansson
|
August 3rd, 2012, 5:56 a.m.
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[Submitted] scons: Restructure ccflags and ldflags
|
ahansson
|
September 10th, 2012, 9:51 a.m.
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[Discarded] mem: Add a FromCache packet attribute
|
ahansson
|
April 9th, 2016, 4:21 p.m.
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[Submitted] mem: Make packet bus-related time accounting relative
|
ahansson
|
February 14th, 2013, 1:52 a.m.
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[Submitted] mem: Add bytes per activate DRAM controller stat
|
ahansson
|
May 11th, 2013, 10:29 a.m.
|
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[Discarded] config: Use BaseSESystem in multi-processor regressions
|
ahansson
|
June 6th, 2013, 2:32 p.m.
|
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[Submitted] alpha: Check interrupts before quiesce
|
ahansson
|
August 5th, 2013, 8:35 a.m.
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[Submitted] kvm: Only include KVM support for supported kernels
|
ahansson
|
September 30th, 2013, 5:34 p.m.
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[Submitted] arm: Panics in miscreg read functions can be tripped by O3 model
|
ahansson
|
April 23rd, 2014, 12:19 p.m.
|
|
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[Submitted] mem: Update DDR3 and DDR4 based on datasheets
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
|
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[Submitted] mem: Refactor assignment of Packet types
|
ahansson
|
August 13th, 2014, 2:07 p.m.
|
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[Submitted] cpu: Add branch predictor PMU probe points
|
ahansson
|
September 29th, 2014, 10:38 a.m.
|
|
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|
[Submitted] scons: Avoid implicit command dependencies
|
ahansson
|
November 30th, 2014, 9:39 a.m.
|
|
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|
[Submitted] mem: Fix bug relating to writebacks and prefetches
|
ahansson
|
December 12th, 2014, 5:49 p.m.
|
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[Submitted] mem: Clarify cache behaviour for pending dirty responses
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
|
|
|
[Submitted] config: Add soak test for memtest.py
|
ahansson
|
March 6th, 2015, 1:39 p.m.
|
|
|
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[Submitted] mem: Snoop into caches on uncacheable accesses
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
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|
[Submitted] CPU: Moving towards a more general port across CPU models
|
ahansson
|
December 19th, 2011, 5:54 a.m.
|
|
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|
[Submitted] Thread: Use inherited baseCpu rather than cpu in SimpleThread
|
ahansson
|
January 27th, 2012, 5:02 a.m.
|
|
|
|
[Submitted] MEM: Prepare mport for master/slave split
|
ahansson
|
February 20th, 2012, 2:55 a.m.
|
|
|
|
[Submitted] mem: Make the coherent crossbar account for timing snoops
|
ahansson
|
August 19th, 2015, 9:06 a.m.
|
|
|
|
[Submitted] MEM: Add a snooping DMA port subclass for table walker
|
ahansson
|
May 17th, 2012, 5:05 a.m.
|
|
|
|
[Submitted] cpu: Encapsulate traffic generator input in a stream
|
ahansson
|
December 6th, 2012, 7:54 p.m.
|
|
|
|
stats: Add version information and timestamp to the SQL database
|
ahansson
|
January 15th, 2013, 10:36 a.m.
|
|
|
|
[Submitted] mem: More descriptive enum names for address mapping
|
ahansson
|
March 28th, 2013, 3:28 a.m.
|
|
|
|
[Submitted] cpu: Block traffic generator when requests have to retry
|
ahansson
|
April 23rd, 2013, 12:29 a.m.
|
|
|
|
[Submitted] config: Rename clock option to Ruby clock
|
ahansson
|
May 24th, 2013, 3:30 a.m.
|
|
|
|
[Discarded] scons: Move the warning about self assignment to SWIG code only
|
ahansson
|
June 28th, 2013, 10:34 a.m.
|
|
|
|
[Submitted] alpha: Move system virtProxy to Alpha only
|
ahansson
|
August 19th, 2013, 9:34 a.m.
|
|
|
|
[Submitted] mem: Use the same timing calculation for DRAM read and write
|
ahansson
|
October 16th, 2013, 7:40 a.m.
|
|
|
|
[Submitted] mem: Track DRAM read/write switching and add hysteresis
|
ahansson
|
March 17th, 2014, 8:16 a.m.
|
|
|
|
[Submitted] cpu: Allow setWhen on trace objects
|
ahansson
|
April 23rd, 2014, 12:24 p.m.
|
|
|
|
[Submitted] mem: DRAMPower trace output
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
|
|
|
[Submitted] base: Use the global Mersenne twister throughout
|
ahansson
|
August 17th, 2014, 10:50 a.m.
|
|
|
|
[Submitted] dev: Add support for 9p proxying over VirtIO
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] config: Add Current as a parameter type
|
ahansson
|
September 29th, 2014, 10:40 a.m.
|
|
|
|
[Submitted] mem: Add const getters for write packet data
|
ahansson
|
November 17th, 2014, 6:13 a.m.
|
|
|
|
[Submitted] x86: Delay X86 table walk on receiving walker response
|
ahansson
|
January 5th, 2015, 4:35 p.m.
|
|
|
|
[Submitted] arm: Wire up the GIC with the platform in the base class
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
