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[Submitted] arm, dev: Add support for listing DMA ports in new platforms
|
andysan
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July 22nd, 2016, 3:05 p.m.
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[Submitted] arm, config: Add initial support for Ruby
|
andysan
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July 22nd, 2016, 3:06 p.m.
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[Discarded] ruby: Size the MI_example directory to cover all phys mem
|
andysan
|
July 22nd, 2016, 3:08 p.m.
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[Submitted] cpu: Add frequency scaling to the Trace CPU
|
andysan
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August 12th, 2016, 4:45 p.m.
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[Submitted] cpu: Adjust for trace offset and fix stats
|
andysan
|
August 12th, 2016, 4:45 p.m.
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[Submitted] cpu: Support exit when any one Trace CPU completes replay
|
andysan
|
August 12th, 2016, 4:45 p.m.
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[Submitted] tests: Add support for functional only tests
|
andysan
|
September 15th, 2016, 5:32 p.m.
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[Submitted] util: git pre-commit hook to check staged files
|
andysan
|
September 15th, 2016, 5:32 p.m.
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[Submitted] Fix: Fix the O3 CPU Drain
|
andysan
|
September 21st, 2016, 2:57 p.m.
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[Submitted] style: Add options to select checkers and apply fixes
|
andysan
|
October 7th, 2016, 3:11 p.m.
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[Submitted] sim: Remove redundant export_method_cxx_predecls
|
andysan
|
December 20th, 2016, 8:07 a.m.
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[Submitted] python: Don't use Swig to cast stats
|
andysan
|
December 20th, 2016, 8:08 a.m.
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[Submitted] python: Move native wrappers to the _m5 namespace
|
andysan
|
December 20th, 2016, 8:10 a.m.
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[Submitted] util: Add maintainer tools to create upstream patches
|
andysan
|
December 21st, 2016, 3:31 p.m.
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[Submitted] style: Force Python.h to be included before main header
|
andysan
|
January 27th, 2017, 1:39 p.m.
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[Submitted] python: Add a generalized mechanism to configure stats
|
andysan
|
February 21st, 2017, 6:53 p.m.
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[Submitted] tests: Disable descriptions in stat files
|
andysan
|
February 21st, 2017, 6:53 p.m.
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[Submitted] base: Refactor logging to make log level selection cleaner
|
andysan
|
February 21st, 2017, 6:54 p.m.
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[Submitted] arch: Include generated decoder header after normal headers
|
andysan
|
February 21st, 2017, 6:55 p.m.
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[Discarded] ext: Add pybind rev f4b81b3
|
andysan
|
February 21st, 2017, 6:55 p.m.
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[Discarded] ext: Fix undefined macro in pybind
|
andysan
|
February 21st, 2017, 6:55 p.m.
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[Discarded] python: Use PyBind11 instead of SWIG for Python wrappers
|
andysan
|
February 21st, 2017, 6:56 p.m.
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[Discarded] power: Avoid forward declarations that confuse wrappers
|
andysan
|
February 21st, 2017, 7:02 p.m.
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[Discarded] gpu-compute: Fix Python/C++ object hierarchy discrepancies
|
andysan
|
February 21st, 2017, 7:02 p.m.
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gpu-compute: Changed stat name for AMD architecture
|
apattnai
|
May 16th, 2016, 9:29 p.m.
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x86: Fix SMT support (zeroReg, TLBs)
|
apellegr
|
June 29th, 2012, 3:15 p.m.
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arm: Implement store-pair (aarch64) as a single micro-op
|
aperais
|
January 26th, 2016, 9 p.m.
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[Submitted] o3: Clarify meaning of cachePorts variable in lsq_unit.hh
|
aperais
|
April 26th, 2016, 12:42 p.m.
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[Submitted] cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)
|
aperais
|
November 17th, 2016, 10:29 a.m.
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[Submitted] cpu: change comments in tournament branch predictor to reflect what the code does
|
aperais
|
November 18th, 2016, 12:41 p.m.
|
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[Submitted] cpu: disallow speculative update of the conditional branch predictor tables (o3)
|
aperais
|
November 18th, 2016, 3:14 p.m.
|
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[Submitted] cpu: implement L-TAGE branch predictor
|
aperais
|
November 22nd, 2016, 2:31 p.m.
|
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[Submitted] arch: [Patch 1/5] Added RISC-V base instruction set RV64I
|
aroelke
|
September 14th, 2016, 10:45 p.m.
|
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[Submitted] riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
|
aroelke
|
September 19th, 2016, 7:12 p.m.
|
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[Submitted] riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD
|
aroelke
|
September 19th, 2016, 7:26 p.m.
|
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[Submitted] riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A
|
aroelke
|
September 19th, 2016, 7:41 p.m.
|
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[Submitted] riscv: [Patch 5/5] Added missing support for timing CPU models
|
aroelke
|
September 19th, 2016, 8:14 p.m.
|
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[Submitted] riscv: [Patch 6/5] Improve Linux emulation for RISC-V
|
aroelke
|
October 14th, 2016, 6:17 p.m.
|
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[Submitted] riscv: [Patch 7/5] Corrected LRSC semantics
|
aroelke
|
November 2nd, 2016, 7:34 p.m.
|
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[Submitted] riscv: [Patch 8/5] Added some regression tests to RISC-V
|
aroelke
|
November 3rd, 2016, 7:36 p.m.
|
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[Submitted] riscv: Fix crash when syscall argument reg index is too high
|
aroelke
|
January 12th, 2017, 9 p.m.
|
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[Submitted] riscv: Remove ECALL tests from insttest
|
aroelke
|
January 12th, 2017, 9:18 p.m.
|
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|
[Discarded] Standard switch fix for multi-core
|
atgutier
|
March 10th, 2011, 1:16 p.m.
|
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[Submitted] sim: Fixes Simulation.py to allow more than 1 core for standard switching.
|
atgutier
|
March 11th, 2011, 12:04 p.m.
|
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[Submitted] stats: add separate stats for insts/ops both globally and per cpu model
|
atgutier
|
January 9th, 2012, 1:50 p.m.
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[Submitted] ARM: implement the ProcessInfo methods
|
atgutier
|
February 20th, 2012, 5:16 p.m.
|
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[Submitted] ARM: fix value of MISCREG_CTR returned by readMiscReg()
|
atgutier
|
March 31st, 2012, 8:35 a.m.
|
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[Submitted] O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
|
atgutier
|
May 25th, 2012, 9:05 a.m.
|
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[Submitted] cpu: prevent switched out CPUs from being initialized in the simple and inorder models.
|
atgutier
|
May 28th, 2012, 10:44 a.m.
|
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[Submitted] configs: add run scripts for ics/gb versions of android and bbench
|
atgutier
|
June 7th, 2012, 7:46 a.m.
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