|
|
[Submitted] mem: Adding stats for DRAM power calculation
|
ahansson
|
October 16th, 2013, 7:49 a.m.
|
|
|
|
[Submitted] mem: Add utility script to plot DRAM efficiency sweep
|
ahansson
|
August 13th, 2014, 12:49 p.m.
|
|
|
|
[Submitted] mem: Add tWR to DRAM activate and precharge constraints
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Add tTAW and tFAW to the SimpleDRAM model
|
ahansson
|
December 6th, 2012, 8:28 p.m.
|
|
|
|
[Submitted] mem: Add tRTP to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
|
|
|
[Submitted] mem: Add tRAS parameter to the DRAM controller model
|
ahansson
|
October 16th, 2013, 7:36 a.m.
|
|
|
|
[Submitted] mem: Add tracing support in the communication monitor
|
ahansson
|
December 6th, 2012, 7:52 p.m.
|
|
|
|
[Submitted] MEM: Add the system port as a central access point
|
ahansson
|
December 19th, 2011, 5:52 a.m.
|
|
|
|
[Submitted] MEM: Add the PortId type and a corresponding id field to Port
|
ahansson
|
April 7th, 2012, 9:51 a.m.
|
|
|
|
[Discarded] MEM: Add the port proxies to the source tree
|
ahansson
|
November 28th, 2011, 10:14 a.m.
|
|
|
|
[Submitted] MEM: Add the communication monitor
|
ahansson
|
April 20th, 2012, 11:23 a.m.
|
|
|
|
[Submitted] mem: Add support for multi-channel DRAM configurations
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Add static latency to the DRAM controller
|
ahansson
|
May 11th, 2013, 10:28 a.m.
|
|
|
|
[Submitted] mem: Add stack distance statistics to the CommMonitor
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] mem: Add snoops for CleanEvicts and Writebacks in atomic mode
|
ahansson
|
August 19th, 2015, 9:07 a.m.
|
|
|
|
[Submitted] mem: Add snoop filters to L2 crossbars, and check size
|
ahansson
|
August 21st, 2015, 3:49 p.m.
|
|
|
|
[Submitted] mem: Add ReadCleanReq and ReadSharedReq packets
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
|
|
[Submitted] mem: Add rank-wise refresh to the DRAM controller
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] mem: Add predecessor to SenderState base class
|
ahansson
|
February 14th, 2013, 1:48 a.m.
|
|
|
|
[Submitted] mem: Add precharge all (PREA) to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] MEM: Add port proxies instead of non-structural ports
|
ahansson
|
December 19th, 2011, 5:53 a.m.
|
|
|
|
[Submitted] mem: Add parameter to reserve MSHR entries for demand access
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] mem: Add PacketInfo to be used for packet probe points
|
ahansson
|
September 25th, 2015, 2:29 p.m.
|
|
|
|
[Submitted] mem: Add optional request flags to the packet trace
|
ahansson
|
March 14th, 2013, 7 a.m.
|
|
|
|
[Submitted] mem: Add option to force in-order insertion in PacketQueue
|
ahansson
|
February 19th, 2015, 7:56 a.m.
|
|
|
|
[Submitted] mem: Add missing stats update for uncacheable MSHRs
|
ahansson
|
March 30th, 2015, 9:16 a.m.
|
|
|
|
[Submitted] mem: Add missig timing and current parameters to DRAM configs
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
|
|
|
[Submitted] mem: Add memory rank-to-rank delay
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] mem: Add MemChecker and MemCheckerMonitor
|
ahansson
|
December 12th, 2014, 5:45 p.m.
|
|
|
|
[Submitted] mem: Add interleaving bits to the address ranges
|
ahansson
|
December 6th, 2012, 8:09 p.m.
|
|
|
|
[Submitted] mem: Add forward snoop check for HardPFReqs
|
ahansson
|
March 30th, 2015, 9:16 a.m.
|
|
|
|
[Submitted] mem: Add ExternalMaster and ExternalSlave ports
|
ahansson
|
September 29th, 2014, 10:46 a.m.
|
|
|
|
[Submitted] mem: Add explicit Cache subclass and make BaseCache abstract
|
ahansson
|
August 13th, 2015, 8:31 p.m.
|
|
|
|
[Submitted] mem: Add DRAMPower wrapping class
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
|
|
|
[Submitted] mem: Add DRAM power states to the controller
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Add DRAM device size and check against config
|
ahansson
|
September 29th, 2014, 10:44 a.m.
|
|
|
|
[Submitted] mem: Add DRAM cycle time
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
|
|
|
|
[Submitted] mem: Add deferred packet class to prefetcher
|
ahansson
|
February 14th, 2013, 1:52 a.m.
|
|
|
|
[Submitted] mem: Add DDR4 bank group timing
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] mem: Add DDR3 and LPDDR2 DRAM controller configurations
|
ahansson
|
December 6th, 2012, 8:31 p.m.
|
|
|
|
[Submitted] mem: Add crossbar latencies
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] mem: Add const getters for write packet data
|
ahansson
|
November 17th, 2014, 6:13 a.m.
|
|
|
|
[Submitted] mem: Add close adaptive paging policy to DRAM controller model
|
ahansson
|
March 7th, 2014, 11:44 p.m.
|
|
|
|
[Submitted] mem: Add CleanEvict and Writeback support to snoop filters
|
ahansson
|
August 19th, 2015, 9:07 a.m.
|
|
|
|
[Submitted] mem: Add clean evicts to improve snoop filter tracking
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
|
|
[Submitted] mem: Add checks and explanation for assertMemInhibit usage
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] mem: Add check if SimpleDRAM nextReqEvent is scheduled
|
ahansson
|
February 19th, 2013, 6:39 a.m.
|
|
|
|
[Submitted] mem: Add check for snooping ports in the snoop filter
|
ahansson
|
August 19th, 2015, 9:07 a.m.
|
|
|
|
[Submitted] mem: Add cache clusivity
|
ahansson
|
October 19th, 2015, 5:02 p.m.
|
|
