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[Submitted] cpu: o3: commit: mark pipeline delay variable as consts
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nilay
|
February 28th, 2015, 10:41 p.m.
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[Submitted] cpu: o3: Remove unused code in iew, add assert instead.
|
nilay
|
March 4th, 2015, 8:41 a.m.
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[Submitted] cpu: o3: another assert instead of check
|
nilay
|
March 4th, 2015, 8:53 a.m.
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[Discarded] mem: fix prefetcher bug regarding write buffer hits
|
stever
|
February 6th, 2015, 12:38 a.m.
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[Submitted] mem: Add byte mask to Packet::checkFunctional
|
ahansson
|
February 19th, 2015, 7:56 a.m.
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[Submitted] mem: Fix cache MSHR conflict determination
|
ahansson
|
February 23rd, 2015, 1:05 p.m.
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[Submitted] mem: Add crossbar latencies
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] mem: Add option to force in-order insertion in PacketQueue
|
ahansson
|
February 19th, 2015, 7:56 a.m.
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[Submitted] mem: Downstream components consumes new crossbar delays
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] mem: Move crossbar default latencies to subclasses
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] dev, arm: Clean up PL011 and rewrite interrupt handling
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] arm: Share a port for the two table walker objects
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] cpu: Add a PC-value to the traffic generator requests
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] tests: Run regression timeout as foreground
|
ahansson
|
February 19th, 2015, 7:55 a.m.
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[Submitted] mem: Fix prefetchSquash + memInhibitAsserted bug
|
ahansson
|
February 13th, 2015, 8:36 a.m.
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[Submitted] cpu: o3 register renaming request handling improved
|
ahansson
|
February 7th, 2015, 5:24 p.m.
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[Submitted] mem: Split port retry for all different packet classes
|
ahansson
|
February 7th, 2015, 5:24 p.m.
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[Submitted] Ruby: Update backing store option to propagate through to all RubyPorts
|
powerjg
|
February 4th, 2015, 11:31 p.m.
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[Discarded] config: Add --sst configuration option
|
cdunham
|
February 20th, 2015, 6:47 p.m.
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[Submitted] config: Add memcheck stress test
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
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[Submitted] mem: Fix initial value problem with MemChecker
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
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[Submitted] dev: Fix undefined behaviuor in i8254xGBe
|
ahansson
|
February 9th, 2015, 2:24 p.m.
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[Submitted] arm: Wire up the GIC with the platform in the base class
|
ahansson
|
February 5th, 2015, 10:59 a.m.
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[Submitted] mem: mmap the backing store with MAP_NORESERVE
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
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[Submitted] mem: Use the range cache for lookup as well as access
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
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[Submitted] arch: Make readMiscRegNoEffect const throughout
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
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[Submitted] config: add --root-device machine parameter
|
ahansson
|
January 28th, 2015, 10:06 a.m.
|
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[Submitted] arm: Merge ISA files with pseudo instructions
|
ahansson
|
December 12th, 2014, 5:45 p.m.
|
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[Submitted] cpu: add support for outputing a protobuf formatted CPU trace
|
ali
|
December 10th, 2014, 5:57 p.m.
|
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[Submitted] mem: Clarification of packet crossbar timings
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
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[Submitted] config: Revamp memtest to allow testers on any level
|
ahansson
|
January 21st, 2015, 1:24 p.m.
|
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[Submitted] cpu: Tidy up the MemTest and make false sharing more obvious
|
ahansson
|
January 21st, 2015, 1:23 p.m.
|
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[Submitted] sim: Move the BaseTLB to src/arch/generic/
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
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[Submitted] base: Do not dereference NULL in CompoundFlag creation
|
ahansson
|
February 5th, 2015, 11:36 a.m.
|
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[Submitted] style: Fix incorrect style checker option name
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
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[Submitted] mem: Clarify usage of latency in the cache
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
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[Submitted] style: Fix broken m5format command
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
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[Submitted] base: Add compiler macros to add deprecation warnings
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
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[Discarded] Ruby: Fix a bug when issuing unaligned writes to memory
|
powerjg
|
February 9th, 2015, 8:23 p.m.
|
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[Submitted] config: make M5_PATH a real search path
|
stever
|
November 24th, 2014, 2:48 a.m.
|
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[Submitted] cpu: Ensure timing CPU sinks response before sending new request
|
ahansson
|
January 27th, 2015, 10:19 a.m.
|
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[Submitted] mem: Clarify express snoop behaviour
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
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[Submitted] mem: Clarify cache behaviour for pending dirty responses
|
ahansson
|
January 26th, 2015, 6:23 p.m.
|
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[Submitted] config: Add XOR hashing to the DRAM channel interleaving
|
ahansson
|
January 21st, 2015, 1:23 p.m.
|
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[Submitted] base: Add XOR-based hashed address interleaving
|
ahansson
|
January 21st, 2015, 1:22 p.m.
|
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[Submitted] config: Adjust DRAM channel interleaving defaults
|
ahansson
|
January 21st, 2015, 1:22 p.m.
|
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[Submitted] scons: Avoid implicit command dependencies
|
ahansson
|
November 30th, 2014, 9:39 a.m.
|
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[Submitted] style: Update the style checker to handle new include order
|
ahansson
|
January 26th, 2015, 5:55 p.m.
|
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[Submitted] config: arm: fix os_flags
|
musleh
|
January 13th, 2015, 8:32 p.m.
|
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[Discarded] mem: Fix race condition in crossbar routing table
|
powerjg
|
January 26th, 2015, 8:28 p.m.
|
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