Review Board 2.0.15


All Review Requests

Summary Submitter
Posted Last Updated
MEM: Enable multiple distributed generalized memories
ahansson
March 21st, 2012, 4:20 p.m.
Bus: Split the bus into a non-coherent and coherent bus
ahansson
May 25th, 2012, 9:47 a.m.
Power: Fix MaxMiscDestRegs which was set to zero
ahansson
June 8th, 2012, 2:54 a.m.
Fix: Address a few benign memory leaks
ahansson
July 6th, 2012, 12:18 a.m.
mem: Explicitly check MSHR snoops for cases not dealt with
ahansson
December 9th, 2015, 11:54 p.m.
Checker: Bump the realview-o3-checker regression
ahansson
August 25th, 2012, 4 a.m.
Mem: Remove the file parameter from AbstractMemory
ahansson
September 10th, 2012, 9:15 a.m.
config: Use shared cache config for regressions
ahansson
October 24th, 2012, 7:13 a.m.
config: Add a check for fastmem only used with Atomic CPU
ahansson
October 25th, 2012, 10:35 a.m.
stats: Fix some bugs in the python based stats system
ahansson
January 29th, 2013, 2:17 a.m.
mem: Add deferred packet class to prefetcher
ahansson
February 14th, 2013, 1:52 a.m.
config: Add a BaseSESystem builder for re-use in regressions
ahansson
June 6th, 2013, 2:30 p.m.
config: Remove Clock parameter multiplication
ahansson
June 11th, 2013, 9:31 a.m.
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
ahansson
March 7th, 2014, 11:47 p.m.
scons: remove vector typemaps obsoleted by SWIG 2.0.4
ahansson
April 23rd, 2014, 12:11 p.m.
mem: Merge DRAM page-management calculations
ahansson
April 23rd, 2014, 12:34 p.m.
arm: ISA X31 destination register fix
ahansson
August 13th, 2014, 2:07 p.m.
mem: Fix a bug in the cache port flow control
ahansson
August 27th, 2014, 4:15 p.m.
sim: Add typedefs for PMU probe points
ahansson
September 29th, 2014, 10:38 a.m.
mem: Rework the structuring of the prefetchers
ahansson
December 12th, 2014, 5:47 p.m.
style: Update the style checker to handle new include order
ahansson
January 26th, 2015, 5:55 p.m.
arm: Add a GICv2m device
ahansson
March 6th, 2015, 1:39 p.m.
mem: Pass shared downstream through caches
ahansson
March 30th, 2015, 9:17 a.m.
MAC: Make gem5 compile and run on MacOSX 10.7.2
ahansson
December 19th, 2011, 5:50 a.m.
gcc: Clean-up of non-C++0x compliant code, first steps
ahansson
March 6th, 2012, 9:20 a.m.
ruby: Move Rubys cache class from Cache.py to RubyCache.py
ahansson
August 13th, 2015, 8:30 p.m.
mem: Clarify cache MSHR handling on fill
ahansson
October 13th, 2015, 3:35 p.m.
swig: Use SWIG from environment when determining version
ahansson
June 20th, 2012, 4:32 p.m.
Bridge: Use EventWrapper instead of Event subclass for sendEvent
ahansson
July 17th, 2012, 11:03 a.m.
mem: Add tracing support in the communication monitor
ahansson
December 6th, 2012, 7:52 p.m.
stats: Optimise SQL stats output to improve speed and file size
ahansson
January 15th, 2013, 10:32 a.m.
mem: Fix SenderState related cache deadlock
ahansson
February 14th, 2013, 6:13 a.m.
cpu: Use request flags in trace playback
ahansson
March 28th, 2013, 3:28 a.m.
cpu: Move traffic generator sending out of generator states
ahansson
April 23rd, 2013, 12:26 a.m.
Alpha specific alignment of PC
ah
December 21st, 2011, 12:15 a.m.
[Discarded] Detailed DDR state machine and power modeler for Ruby
agarwalshivam
November 14th, 2013, 9:04 a.m.
ARM: Enable Ruby functionality with ARM FS
afc32
May 12th, 2012, 4:23 p.m.
arm, config: Enabled MemConfig usage for the example big.LITTLE
abutko
October 14th, 2016, 7:40 a.m.
arm, config: added support for ex5 model of big.LITTLE
abutko
October 14th, 2016, 7:41 a.m.
[Discarded] arm, config: [2/2] added support for ex5 model of big.LITTLE
abutko
October 17th, 2016, 3:32 a.m.
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