Review Board 2.0.15


All Review Requests

Summary
Submitter
Posted Last Updated
mem: Split WriteInvalidateReq into write and invalidate
ahansson
June 10th, 2015, 7:59 a.m.
MEM: Split SimpleTimingPort into PacketQueue and ports
ahansson
February 27th, 2012, 2:29 a.m.
mem: Split port retry for all different packet classes
ahansson
February 7th, 2015, 5:24 p.m.
mem: Snoop into caches on uncacheable accesses
ahansson
March 30th, 2015, 9:17 a.m.
mem: Skip address mapper range checks to allow more flexibility
ahansson
December 6th, 2012, 8:02 p.m.
MEM: Simplify ports by removing EventManager
ahansson
December 19th, 2011, 5:55 a.m.
mem: Simplify DRAM response scheduling
ahansson
April 23rd, 2014, 12:36 p.m.
MEM: Simplify cache ports preparing for master/slave split
ahansson
February 21st, 2012, 3:21 a.m.
mem: Simplify cache packet handling for uncacheable writes
ahansson
March 31st, 2016, 6:19 p.m.
mem: SimpleDRAM variable naming and whitespace fixes
ahansson
February 19th, 2013, 6:38 a.m.
mem: Simple Snoop Filter
ahansson
September 10th, 2014, 7:53 a.m.
mem: Set the cache line size on a system level
ahansson
July 12th, 2013, 3:06 p.m.
mem: Separate waiting for the bus and waiting for a peer
ahansson
March 14th, 2013, 7:02 a.m.
mem: Separate the two snoop response cases in the bus
ahansson
April 22nd, 2013, 3:34 p.m.
Mem: Separate the host and guest views of memory backing store
ahansson
September 11th, 2012, 11:20 a.m.
MEM: Separate snoops and normal memory requests/responses
ahansson
April 2nd, 2012, 6:49 a.m.
MEM: Separate requests and responses for timing accesses
ahansson
April 11th, 2012, 8:23 a.m.
MEM: Separate queries for snooping and address ranges
ahansson
December 19th, 2011, 5:58 a.m.
mem: Schedule time for DRAM event taking tRAS into account
ahansson
October 16th, 2013, 7:38 a.m.
mem: Rework the structuring of the prefetchers
ahansson
December 12th, 2014, 5:47 p.m.
mem: Replace check with panic where inhibited should not happen
ahansson
March 28th, 2013, 3:26 a.m.
mem: Reorganize cache tags and make them a SimObject
ahansson
June 20th, 2013, 5:47 p.m.
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
ahansson
March 7th, 2014, 11:47 p.m.
mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED
ahansson
March 17th, 2015, 7:08 p.m.
mem: Rename Bus to XBar to better reflect its behaviour
ahansson
September 10th, 2014, 7:54 a.m.
MEM: Removing the default port peer from Python ports
ahansson
December 23rd, 2011, 1:36 a.m.
mem: Remove WriteInvalidate support
ahansson
November 25th, 2014, 9:48 a.m.
mem: Remove unused RequestState in the bridge
ahansson
January 5th, 2015, 4:53 p.m.
mem: Remove unused RequestCause in cache
ahansson
July 13th, 2015, 3:17 p.m.
mem: Remove unused Packet src and dest fields
ahansson
January 12th, 2015, 4:10 p.m.
mem: Remove unused cache stats
ahansson
February 24th, 2016, 9:29 a.m.
mem: Remove unused cache squash functionality
ahansson
August 13th, 2015, 8:31 p.m.
mem: Remove unused cache squash functionality
ahansson
December 9th, 2015, 11:52 p.m.
MEM: Remove the otherPort from the cache ports
ahansson
January 18th, 2012, 2:33 a.m.
MEM: Remove the notion of the default port
ahansson
December 19th, 2011, 5:56 a.m.
mem: Remove the joining of neighbouring ranges
ahansson
December 6th, 2012, 8:01 p.m.
mem: Remove the GHB prefetcher from the source tree
ahansson
September 10th, 2014, 7:51 a.m.
MEM: Remove the functional ports from the memory system
ahansson
December 19th, 2011, 6 a.m.
Mem: Remove the file parameter from AbstractMemory
ahansson
September 10th, 2012, 9:15 a.m.
mem: Remove the cache builder
ahansson
May 23rd, 2013, 12:44 a.m.
MEM: Remove the Broadcast destination from the packet
ahansson
April 4th, 2012, 12:52 a.m.
mem: Remove templates in cache model
ahansson
March 30th, 2015, 9:16 a.m.
[Discarded] mem: Remove RubyMemoryControl and rely on DRAMCtrl
ahansson
April 2nd, 2015, 9:31 a.m.
mem: Remove redundant Packet::allocate calls
ahansson
November 17th, 2014, 6:14 a.m.
mem: Remove redundant is_top_level cache parameter
ahansson
June 10th, 2015, 7:59 a.m.
mem: Remove redundant allocateUncachedReadBuffer in cache
ahansson
March 17th, 2015, 7:09 p.m.
mem: Remove printing of DRAM params
ahansson
April 23rd, 2014, 12:36 p.m.
MEM: Remove Port removeConn and MemObject deletePortRefs
ahansson
December 19th, 2011, 5:57 a.m.
mem: Remove Packet source from ForwardResponseRecord
ahansson
January 12th, 2015, 4:09 p.m.
MEM: Remove onRetryList from BusPort and rely on retryList
ahansson
January 18th, 2012, 2:29 a.m.
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