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[Submitted] mem: Add MemChecker and MemCheckerMonitor
|
ahansson
|
December 12th, 2014, 5:45 p.m.
|
|
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[Submitted] mem: Add memory rank-to-rank delay
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
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[Submitted] mem: Add missig timing and current parameters to DRAM configs
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
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[Submitted] mem: Add missing stats update for uncacheable MSHRs
|
ahansson
|
March 30th, 2015, 9:16 a.m.
|
|
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[Submitted] mem: Add option to force in-order insertion in PacketQueue
|
ahansson
|
February 19th, 2015, 7:56 a.m.
|
|
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[Submitted] mem: Add optional request flags to the packet trace
|
ahansson
|
March 14th, 2013, 7 a.m.
|
|
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[Submitted] mem: Add PacketInfo to be used for packet probe points
|
ahansson
|
September 25th, 2015, 2:29 p.m.
|
|
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[Submitted] mem: Add parameter to reserve MSHR entries for demand access
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] MEM: Add port proxies instead of non-structural ports
|
ahansson
|
December 19th, 2011, 5:53 a.m.
|
|
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[Submitted] mem: Add precharge all (PREA) to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
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[Submitted] mem: Add predecessor to SenderState base class
|
ahansson
|
February 14th, 2013, 1:48 a.m.
|
|
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|
[Submitted] mem: Add rank-wise refresh to the DRAM controller
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] mem: Add ReadCleanReq and ReadSharedReq packets
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
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|
[Submitted] mem: Add snoop filters to L2 crossbars, and check size
|
ahansson
|
August 21st, 2015, 3:49 p.m.
|
|
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|
[Submitted] mem: Add snoops for CleanEvicts and Writebacks in atomic mode
|
ahansson
|
August 19th, 2015, 9:07 a.m.
|
|
|
|
[Submitted] mem: Add stack distance statistics to the CommMonitor
|
ahansson
|
December 12th, 2014, 5:46 p.m.
|
|
|
|
[Submitted] mem: Add static latency to the DRAM controller
|
ahansson
|
May 11th, 2013, 10:28 a.m.
|
|
|
|
[Submitted] mem: Add support for multi-channel DRAM configurations
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] MEM: Add the communication monitor
|
ahansson
|
April 20th, 2012, 11:23 a.m.
|
|
|
|
[Discarded] MEM: Add the port proxies to the source tree
|
ahansson
|
November 28th, 2011, 10:14 a.m.
|
|
|
|
[Submitted] MEM: Add the PortId type and a corresponding id field to Port
|
ahansson
|
April 7th, 2012, 9:51 a.m.
|
|
|
|
[Submitted] MEM: Add the system port as a central access point
|
ahansson
|
December 19th, 2011, 5:52 a.m.
|
|
|
|
[Submitted] mem: Add tracing support in the communication monitor
|
ahansson
|
December 6th, 2012, 7:52 p.m.
|
|
|
|
[Submitted] mem: Add tRAS parameter to the DRAM controller model
|
ahansson
|
October 16th, 2013, 7:36 a.m.
|
|
|
|
[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
|
|
|
[Submitted] mem: Add tRTP to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Add tTAW and tFAW to the SimpleDRAM model
|
ahansson
|
December 6th, 2012, 8:28 p.m.
|
|
|
|
[Submitted] mem: Add tWR to DRAM activate and precharge constraints
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Add utility script to plot DRAM efficiency sweep
|
ahansson
|
August 13th, 2014, 12:49 p.m.
|
|
|
|
[Submitted] mem: Adding stats for DRAM power calculation
|
ahansson
|
October 16th, 2013, 7:49 a.m.
|
|
|
|
[Submitted] mem: Adding verbose debug output in the memory system
|
ahansson
|
March 14th, 2013, 7:05 a.m.
|
|
|
|
[Submitted] mem: Address mapping with fine-grained channel interleaving
|
ahansson
|
March 28th, 2013, 3:28 a.m.
|
|
|
|
[Submitted] mem: Adjust cache queue reserve to more conservative values
|
ahansson
|
February 24th, 2016, 9:28 a.m.
|
|
|
|
[Discarded] mem: Adopt a more sensible cache class hierarchy
|
ahansson
|
February 24th, 2016, 9:29 a.m.
|
|
|
|
[Submitted] mem: Align all MSHR entries to block boundaries
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
|
|
[Submitted] mem: Align cache behaviour in atomic when upstream is responding
|
ahansson
|
January 1st, 2016, 2:16 p.m.
|
|
|
|
[Submitted] mem: Align cache timing to clock edges
|
ahansson
|
June 4th, 2013, 10:46 a.m.
|
|
|
|
[Submitted] mem: Align downstream cache packet creation in atomic and timing
|
ahansson
|
March 31st, 2016, 6:21 p.m.
|
|
|
|
[Submitted] mem: Align how snoops are handled when hitting writebacks
|
ahansson
|
December 30th, 2015, 7:11 p.m.
|
|
|
|
[Discarded] mem: Align rules for sinking packets at the slave
|
ahansson
|
October 26th, 2015, 6:14 p.m.
|
|
|
|
[Submitted] mem: Allocate cache writebacks before new MSHRs
|
ahansson
|
March 22nd, 2015, 7:35 a.m.
|
|
|
|
[Submitted] mem: Allow disabling of tXAW through a 0 activation limit
|
ahansson
|
July 12th, 2013, 9:46 a.m.
|
|
|
|
[Submitted] mem: Allow read-only caches and check compliance
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
|
|
[Submitted] mem: Always use SenderState for response routing in RubyPort
|
ahansson
|
January 5th, 2015, 4:50 p.m.
|
|
|
|
[Submitted] mem: Assume all dynamic packet data is array allocated
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] mem: Auto-generate CommMonitor trace file names
|
ahansson
|
April 23rd, 2014, 12:19 p.m.
|
|
|
|
[Submitted] mem: Avoid DRAM write queue iteration for merging and read lookup
|
ahansson
|
April 24th, 2015, 4:32 p.m.
|
|
|
|
[Submitted] mem: Avoid explicitly zeroing the memory backing store
|
ahansson
|
April 22nd, 2013, 2:44 p.m.
|
|
|
|
[Submitted] mem: Avoid setting markPending if not needed
|
ahansson
|
August 31st, 2015, 9:20 a.m.
|
|
|
|
[Submitted] mem: Be less conservative in clearing load locks in the cache
|
ahansson
|
January 21st, 2016, 6:12 p.m.
|
|
