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[Submitted] kvm, arm: Add support for aarch64
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andysan
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May 18th, 2015, 12:35 p.m.
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[Submitted] sim: Fix broken event unserialization
|
andysan
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June 8th, 2015, 5:05 p.m.
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[Submitted] dev: Implement a simple display timing generator
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andysan
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July 8th, 2015, 12:44 p.m.
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[Submitted] sim: Remove unused SerializeBuilder interface
|
andysan
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August 19th, 2015, 2:42 p.m.
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[Submitted] arm: Don't report the boot ROM as a memory in config tables
|
andysan
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July 22nd, 2016, 3:04 p.m.
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[Submitted] style: Add options to select checkers and apply fixes
|
andysan
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October 7th, 2016, 3:11 p.m.
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[Submitted] dev: Clean up MC146818 register (A & B) handling
|
andysan
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May 2nd, 2013, 3:16 a.m.
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[Submitted] cpu: Add support for scheduling multiple inst/load stop events
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andysan
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June 3rd, 2013, 5:26 a.m.
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[Submitted] kvm: Add support for thread-specific instruction events
|
andysan
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September 19th, 2013, 3:57 p.m.
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[Submitted] base: Use constexpr in Cycles
|
andysan
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June 17th, 2015, 6:43 a.m.
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[Submitted] arm: Correctly check FP/SIMD access permission in aarch32
|
andysan
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May 27th, 2016, 2:04 p.m.
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[Submitted] mem: Update mostly exclusive cache policy to cover more cases
|
andysan
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July 12th, 2016, 7:14 a.m.
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[Submitted] style: Force Python.h to be included before main header
|
andysan
|
January 27th, 2017, 1:39 p.m.
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[Discarded] arch: Use ASI 0xFF instead of bit 63 to for generic IPRs
|
andysan
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October 3rd, 2013, 1:21 p.m.
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[Submitted] base: Add a warn_if macro
|
andysan
|
June 8th, 2015, 11:32 a.m.
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[Submitted] sim: Split ClockedObject to make it usable to non-SimObjects
|
andysan
|
July 7th, 2015, 3:13 p.m.
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[Submitted] dev, arm: Add a platform with support for both aarch32 and aarch64
|
andysan
|
December 5th, 2015, 12:52 a.m.
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[Submitted] kvm: Shutdown KVM and disconnect performance counters on fork
|
andysan
|
January 14th, 2016, 6:31 p.m.
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[Submitted] style: Add a style checker that doesn't depend on Mercurial
|
andysan
|
March 16th, 2016, 11:44 a.m.
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[Submitted] scons: Use the new test framework from scons
|
andysan
|
April 28th, 2016, 3:21 p.m.
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[Submitted] kvm: Initial x86 support
|
andysan
|
September 10th, 2013, 1:33 p.m.
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[Submitted] kvm: Clean up signal handling
|
andysan
|
March 6th, 2014, 12:28 p.m.
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[Submitted] arm: Refactor the TLB test interface
|
andysan
|
March 8th, 2016, 2:04 p.m.
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[Submitted] arch: Include generated decoder header after normal headers
|
andysan
|
February 21st, 2017, 6:55 p.m.
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gpu-compute: Changed stat name for AMD architecture
|
apattnai
|
May 16th, 2016, 9:29 p.m.
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x86: Fix SMT support (zeroReg, TLBs)
|
apellegr
|
June 29th, 2012, 3:15 p.m.
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[Submitted] cpu: change comments in tournament branch predictor to reflect what the code does
|
aperais
|
November 18th, 2016, 12:41 p.m.
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[Submitted] cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)
|
aperais
|
November 17th, 2016, 10:29 a.m.
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[Submitted] cpu: implement L-TAGE branch predictor
|
aperais
|
November 22nd, 2016, 2:31 p.m.
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arm: Implement store-pair (aarch64) as a single micro-op
|
aperais
|
January 26th, 2016, 9 p.m.
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[Submitted] o3: Clarify meaning of cachePorts variable in lsq_unit.hh
|
aperais
|
April 26th, 2016, 12:42 p.m.
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[Submitted] cpu: disallow speculative update of the conditional branch predictor tables (o3)
|
aperais
|
November 18th, 2016, 3:14 p.m.
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[Submitted] riscv: Remove ECALL tests from insttest
|
aroelke
|
January 12th, 2017, 9:18 p.m.
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[Submitted] riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A
|
aroelke
|
September 19th, 2016, 7:41 p.m.
|
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[Submitted] riscv: [Patch 5/5] Added missing support for timing CPU models
|
aroelke
|
September 19th, 2016, 8:14 p.m.
|
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[Submitted] arch: [Patch 1/5] Added RISC-V base instruction set RV64I
|
aroelke
|
September 14th, 2016, 10:45 p.m.
|
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[Submitted] riscv: [Patch 7/5] Corrected LRSC semantics
|
aroelke
|
November 2nd, 2016, 7:34 p.m.
|
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[Submitted] riscv: [Patch 8/5] Added some regression tests to RISC-V
|
aroelke
|
November 3rd, 2016, 7:36 p.m.
|
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[Submitted] riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
|
aroelke
|
September 19th, 2016, 7:12 p.m.
|
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[Submitted] riscv: [Patch 6/5] Improve Linux emulation for RISC-V
|
aroelke
|
October 14th, 2016, 6:17 p.m.
|
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[Submitted] riscv: Fix crash when syscall argument reg index is too high
|
aroelke
|
January 12th, 2017, 9 p.m.
|
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[Submitted] riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD
|
aroelke
|
September 19th, 2016, 7:26 p.m.
|
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[Submitted] x86: x86 instruction-implementation bug fixes
|
atgutier
|
May 11th, 2015, 10:18 p.m.
|
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[Submitted] config: add base class for ruby controllers
|
atgutier
|
May 11th, 2015, 10:23 p.m.
|
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[Submitted] config: set drive_sys.clk_domain.voltage_domain
|
atgutier
|
February 27th, 2014, 3:52 a.m.
|
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[Submitted] slicc: support for arbitrary DPRINTF flags (not just RubySlicc)
|
atgutier
|
May 11th, 2015, 10:20 p.m.
|
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[Submitted] sim: fix overflow check in simulate because Tick is now unsigned
|
atgutier
|
August 21st, 2012, 1:30 p.m.
|
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[Submitted] gpu-compute: Adding vector register file debug messages
|
atgutier
|
June 29th, 2016, 4:02 p.m.
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[Submitted] gpu-compute: add instruction mix stats for the gpu
|
atgutier
|
October 7th, 2016, 9:03 p.m.
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[Submitted] ruby: cleaner ruby tester support
|
atgutier
|
May 11th, 2015, 9:39 p.m.
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