Review Board 2.0.15


Review requests for Default

Summary
Submitter
Posted Last Updated
arch, base, dev, kern, sym: FreeBSD support
bukinr
April 17th, 2015, 1:35 p.m.
[Discarded] arch: do not set Linux-specific AT elf relocation types on FreeBSD
bukinr
April 9th, 2015, 4:42 p.m.
arch: fix build under MacOSX
bukinr
May 6th, 2015, 1:32 p.m.
[Discarded] arch: move argsInit() from ArmLiveProcess class to ArmLinuxProcess32/64 classes
bukinr
April 11th, 2015, 12:53 p.m.
base: fix FreeBSD OS detection
bukinr
April 9th, 2015, 9:37 a.m.
base: fix includes for FreeBSD
bukinr
April 9th, 2015, 9:07 a.m.
base: include header file for FreeBSD
bukinr
April 9th, 2015, 9:29 a.m.
Correct the endianess detection
bukinr
March 27th, 2015, 2 p.m.
dev: dont panic on GIC_EOIR
bukinr
April 9th, 2015, 9:51 a.m.
Extend access width for IDE control registers
bukinr
March 25th, 2015, 11:10 a.m.
scons: specify swig binary filename in env
bukinr
April 30th, 2015, 1:42 p.m.
[ARM] adding support for Ruby memory system
butko
June 6th, 2012, 8:39 a.m.
[Discarded] [ARM] Full System simulation up to 8 cores
butko
June 6th, 2012, 8:50 a.m.
o3: Create quiesce Events with 0ns or 0 cycles
castilloe
April 16th, 2015, 4:45 p.m.
ruby: Fixed a deadlock when restoring a checkpoint with garnet
castilloe
October 30th, 2013, 1:04 p.m.
ruby: Fixes clock domains in configuration files.
castilloe
March 31st, 2014, 10:52 a.m.
X86 : fxsave and fxrestore missing template code
castilloe
August 25th, 2014, 2:20 p.m.
config, mem: add command-line options for L2 MSHR queue size and hit latency
cataldo
June 3rd, 2016, 9:03 p.m.
config, mem: new L2 cache architectures for the classic memory system
cataldo
June 17th, 2016, 3:03 p.m.
dev: Prevent intel 8254 timer events firing before startup
cdirik
December 4th, 2014, 7:14 p.m.
dev: Prevent MC146818 timer RTC events firing before startup
cdirik
November 28th, 2014, 8:57 p.m.
python: Adding event queue empty check after instantiation before startup
cdirik
December 4th, 2014, 6:45 p.m.
arm, config: Add an example ARM big.LITTLE(tm) configuration script
cdunham
July 8th, 2016, 10:28 a.m.
[Discarded] arm, config: Fixups for the example big.LITTLE(tm) configuration
cdunham
August 16th, 2016, 1:56 p.m.
arm, kvm: Automatically use the MuxingKvmGic
cdunham
January 17th, 2017, 10:04 p.m.
arm, kvm: implement MuxingKvmGic
cdunham
January 17th, 2017, 10:04 p.m.
arm, kvm: remove KvmGic
cdunham
January 17th, 2017, 10:04 p.m.
arm: Add AArch64 hypervisor call instruction 'hvc'
cdunham
June 21st, 2016, 1:41 p.m.
arm: Add check to fault routing for hypervisor/virtualization
cdunham
June 21st, 2016, 1:41 p.m.
arm: add stage2 translation support
cdunham
June 21st, 2016, 1:41 p.m.
arm: Add TLBI instruction for stage 2 IPA's
cdunham
June 21st, 2016, 1:41 p.m.
arm: bank GIC registers per CPU
cdunham
July 18th, 2016, 3:26 p.m.
arm: change instruction classes to catch hyp traps
cdunham
June 21st, 2016, 1:41 p.m.
arm: Change TLB software caching
cdunham
July 30th, 2015, 6:47 p.m.
arm: Check TLB stage 2 permissions in AArch64
cdunham
June 21st, 2016, 1:41 p.m.
arm: correctly assign faulting IPA's to HPFAR_EL2
cdunham
June 21st, 2016, 1:41 p.m.
arm: enable EL2 support
cdunham
June 21st, 2016, 1:41 p.m.
arm: Fix EL perceived at TLB for address translation instructions
cdunham
June 21st, 2016, 1:41 p.m.
arm: Fix secure state checking in various places
cdunham
June 21st, 2016, 1:41 p.m.
arm: Fix stage 2 determination in table walker
cdunham
June 21st, 2016, 1:41 p.m.
arm: Fix stage 2 memory attribute checking in AArch64
cdunham
June 21st, 2016, 1:41 p.m.
arm: Fix trapping to Hypervisor during MSR/MRS read/write
cdunham
June 21st, 2016, 1:41 p.m.
arm: invalidate TLB miscreg cache on modification of HSCTLR
cdunham
June 21st, 2016, 1:41 p.m.
arm: Refactor aarch64 table walk logic to remove redundancy
cdunham
June 21st, 2016, 1:41 p.m.
arm: refactor page table walking
cdunham
June 21st, 2016, 1:41 p.m.
arm: s/ctx_id/ctx/ the GIC
cdunham
July 18th, 2016, 3:26 p.m.
arm: Squash after returning from exceptions in v7
cdunham
February 10th, 2016, 12:04 a.m.
arm: tweak MPIDR setting when using SMT
cdunham
July 30th, 2015, 6:47 p.m.
arm: warn not fail on use of missing miscreg CNTHCTL_EL2
cdunham
June 21st, 2016, 1:41 p.m.
base: Add total() to Vector2D stat
cdunham
May 31st, 2016, 10:43 a.m.
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