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[Submitted] mem: Add DRAM power states to the controller
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ahansson
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April 23rd, 2014, 12:34 p.m.
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[Submitted] base: Replace the internal varargs stuff with C++11 constructs
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ahansson
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August 13th, 2014, 12:51 p.m.
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[Submitted] arch: Cleanup unused ISA traits constants
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ahansson
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August 22nd, 2014, 8:17 a.m.
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[Submitted] mem: Add a simple snoop counter per bus
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ahansson
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September 10th, 2014, 7:53 a.m.
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[Submitted] scons: create dummy target to have SWIG generate C++ classes
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ahansson
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September 29th, 2014, 10:37 a.m.
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[Submitted] mem: Add ExternalMaster and ExternalSlave ports
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ahansson
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September 29th, 2014, 10:46 a.m.
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[Submitted] mem: Relax packet src/dest check and shift onus to crossbar
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ahansson
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November 17th, 2014, 6:17 a.m.
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[Submitted] mem: Remove WriteInvalidate support
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ahansson
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November 25th, 2014, 9:48 a.m.
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[Submitted] config: Add --memchecker option
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ahansson
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December 12th, 2014, 5:45 p.m.
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[Submitted] arm, dev: Add a NAND flash timing model
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ahansson
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March 27th, 2015, 1:56 p.m.
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[Submitted] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
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ahansson
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January 18th, 2012, 2:35 a.m.
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[Submitted] MEM: Separate snoops and normal memory requests/responses
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ahansson
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April 2nd, 2012, 6:49 a.m.
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[Submitted] mem: Move cache_impl.hh to cache.cc
|
ahansson
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August 13th, 2015, 8:29 p.m.
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[Submitted] mem: Avoid setting markPending if not needed
|
ahansson
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August 31st, 2015, 9:20 a.m.
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[Submitted] mem: Clarify cache MSHR handling on fill
|
ahansson
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October 13th, 2015, 3:35 p.m.
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[Submitted] Bus: Make the default bus width 8 bytes instead of 64
|
ahansson
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June 11th, 2012, 7:44 a.m.
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[Submitted] Config: Use clock option in se/fs script and pass to switch_cpus
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ahansson
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July 10th, 2012, 4:14 a.m.
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[Submitted] PacketQueue: Allow queuing in the same tick as desired send tick
|
ahansson
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August 3rd, 2012, 9:29 a.m.
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[Submitted] AddrRange: Simplify AddrRange params Python hierarchy
|
ahansson
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August 29th, 2012, 11:52 a.m.
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[Submitted] Checkpoint: Pass maxtick to avoid undefined variable
|
ahansson
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September 11th, 2012, 9:19 a.m.
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[Submitted] Configs: Set the memtest clock to a reasonable value
|
ahansson
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September 28th, 2012, 6:17 a.m.
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stats: Add SQLite database as an output format
|
ahansson
|
January 15th, 2013, 10:26 a.m.
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[Submitted] scons: Fix up numerous warnings about name shadowing
|
ahansson
|
February 14th, 2013, 1:53 a.m.
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[Submitted] mem: Avoid explicitly zeroing the memory backing store
|
ahansson
|
April 22nd, 2013, 2:44 p.m.
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[Submitted] mem: Squash prefetch requests from downstream caches
|
ahansson
|
April 23rd, 2014, 12:21 p.m.
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[Submitted] mem: Remove the GHB prefetcher from the source tree
|
ahansson
|
September 10th, 2014, 7:51 a.m.
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[Submitted] mem: Dynamically determine page bytes in memory components
|
ahansson
|
September 29th, 2014, 10:39 a.m.
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[Submitted] config: add --root-device machine parameter
|
ahansson
|
January 28th, 2015, 10:06 a.m.
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[Submitted] arm: Relax ordering for some uncacheable accesses
|
ahansson
|
March 30th, 2015, 9:17 a.m.
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[Submitted] MEM: Separate queries for snooping and address ranges
|
ahansson
|
December 19th, 2011, 5:58 a.m.
|
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[Submitted] MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
|
ahansson
|
January 29th, 2012, 10:49 a.m.
|
|
|
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[Discarded] Cache: Remove redundant check for uncacheable snoops
|
ahansson
|
May 18th, 2012, 9:12 a.m.
|
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[Discarded] mem: Align rules for sinking packets at the slave
|
ahansson
|
October 26th, 2015, 6:14 p.m.
|
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[Submitted] Packet: Remove NACKs from packet and its use in endpoints
|
ahansson
|
July 21st, 2012, 5:11 a.m.
|
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[Submitted] configs: Make the default memtest behaviour more complex
|
ahansson
|
December 9th, 2015, 11:51 p.m.
|
|
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[Submitted] AddrRange: Transition from Range<T> to AddrRange
|
ahansson
|
September 3rd, 2012, 9:22 p.m.
|
|
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[Submitted] Fix: Address a few minor issues identified by cppcheck
|
ahansson
|
October 12th, 2012, 1:38 a.m.
|
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[Submitted] mem: Skip address mapper range checks to allow more flexibility
|
ahansson
|
December 6th, 2012, 8:02 p.m.
|
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[Submitted] mem: Add support for multi-channel DRAM configurations
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
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[Submitted] cpu: Remove CpuPort and use MasterPort in the CPU classes
|
ahansson
|
March 14th, 2013, 7 a.m.
|
|
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|
[Submitted] sim: Make MaxTick in Python match the one in C++
|
ahansson
|
July 12th, 2013, 9:41 a.m.
|
|
|
|
[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (2/2)
|
ahansson
|
August 19th, 2013, 9:41 a.m.
|
|
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[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
|
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[Submitted] cpu: Useful getters for ActivityRecorder
|
ahansson
|
April 23rd, 2014, 12:26 p.m.
|
|
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[Submitted] power: Add basic DVFS support for gem5
|
ahansson
|
June 11th, 2014, 5:03 p.m.
|
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[Submitted] config: Update Streamline scripts and configs
|
ahansson
|
August 20th, 2014, 8:35 a.m.
|
|
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[Submitted] energy: Small extentions and fixes for DVFS handler
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] mem: Add DRAMPower wrapping class
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
|
|
|
[Submitted] mem: Assume all dynamic packet data is array allocated
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] mem: Clarify usage of latency in the cache
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
