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[Discarded] Changes to the gem5 memory-system (release-0.2)
|
ahansson
|
August 5th, 2011, 10:13 a.m.
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[Discarded] Changes to the gem5 memory-system (release-0.1)
|
ahansson
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July 15th, 2011, 9:03 a.m.
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[Discarded] Cache: Remove redundant check for uncacheable snoops
|
ahansson
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May 18th, 2012, 9:12 a.m.
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[Submitted] Cache: Remove dangling doWriteback declaration
|
ahansson
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May 23rd, 2012, 6:30 a.m.
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[Submitted] Bus: Turn the PortId into a transport function parameter
|
ahansson
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May 23rd, 2012, 6:34 a.m.
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[Submitted] Bus: Split the bus into separate request/response layers
|
ahansson
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June 11th, 2012, 6:56 a.m.
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[Submitted] Bus: Split the bus into a non-coherent and coherent bus
|
ahansson
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May 25th, 2012, 9:47 a.m.
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[Submitted] Bus: Replace tickNextIdle and inRetry with a state variable
|
ahansson
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June 8th, 2012, 10:54 a.m.
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[Submitted] Bus: Remove redundant packet parameter from isOccupied
|
ahansson
|
May 25th, 2012, 9:47 a.m.
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[Submitted] Bus: Make the default bus width 8 bytes instead of 64
|
ahansson
|
June 11th, 2012, 7:44 a.m.
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[Submitted] Bus: Add a notion of layers to the buses
|
ahansson
|
June 11th, 2012, 3:35 a.m.
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[Submitted] Bridge: Use EventWrapper instead of Event subclass for sendEvent
|
ahansson
|
July 17th, 2012, 11:03 a.m.
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[Submitted] Bridge: Split deferred request, response and sender state
|
ahansson
|
May 23rd, 2012, 6:31 a.m.
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[Submitted] Bridge: Remove NACKs in the bridge and unify with packet queue
|
ahansson
|
July 21st, 2012, 5:09 a.m.
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[Submitted] base: Use the global Mersenne twister throughout
|
ahansson
|
August 17th, 2014, 10:50 a.m.
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[Submitted] base: Use STL C++11 random number generation
|
ahansson
|
August 17th, 2014, 10:51 a.m.
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[Submitted] base: Use shared_ptr for stat Node
|
ahansson
|
September 29th, 2014, 10:39 a.m.
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[Submitted] base: Transition CP annotate to use shared_ptr
|
ahansson
|
September 29th, 2014, 10:39 a.m.
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[Submitted] base: Replace the internal varargs stuff with C++11 constructs
|
ahansson
|
August 13th, 2014, 12:51 p.m.
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[Submitted] base: Reimplement the DPRINTF mechanism in a Logger class
|
ahansson
|
September 29th, 2014, 10:45 a.m.
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[Submitted] base: Encapsulate the underlying fields in AddrRange
|
ahansson
|
October 30th, 2012, 8:57 a.m.
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[Submitted] base: Do not dereference NULL in CompoundFlag creation
|
ahansson
|
February 5th, 2015, 11:36 a.m.
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[Submitted] base: Clean up redundant string functions and use C++11
|
ahansson
|
September 10th, 2014, 7:51 a.m.
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[Submitted] base: Avoid size limitation on protobuf coded streams
|
ahansson
|
April 22nd, 2013, 2:43 p.m.
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[Submitted] base: Allow multiple interleaved ranges
|
ahansson
|
May 8th, 2015, 1:10 p.m.
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[Submitted] base: Add XOR-based hashed address interleaving
|
ahansson
|
January 21st, 2015, 1:22 p.m.
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[Submitted] base: Add wrapped protobuf output streams
|
ahansson
|
December 6th, 2012, 7:51 p.m.
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[Submitted] base: Add wrapped protobuf input stream
|
ahansson
|
December 6th, 2012, 7:53 p.m.
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[Submitted] base: Add support for merging of interleaved address ranges
|
ahansson
|
December 6th, 2012, 8:14 p.m.
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[Submitted] base: Add getSectionNames to IniFile
|
ahansson
|
September 10th, 2014, 7:51 a.m.
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[Submitted] base: Add compiler macros to add deprecation warnings
|
ahansson
|
February 5th, 2015, 10:59 a.m.
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[Submitted] base: Add compiler macros for C++11 final/override
|
ahansson
|
August 13th, 2014, 12:50 p.m.
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[Submitted] Atomic: Remove the physmem_port and access memory directly
|
ahansson
|
March 20th, 2012, 10:30 a.m.
|
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[Submitted] arm: Wire up the GIC with the platform in the base class
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
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[Submitted] arm: Use table walker clock that is inherited from CPU
|
ahansson
|
October 23rd, 2012, 2:25 a.m.
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[Submitted] arm: use condition code registers for ARM ISA
|
ahansson
|
August 13th, 2014, 2:07 p.m.
|
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[Submitted] arm: Support >2GB of memory for AArch64 systems
|
ahansson
|
August 20th, 2014, 8:35 a.m.
|
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[Submitted] arm: support 16kb vm granules
|
ahansson
|
August 13th, 2014, 12:50 p.m.
|
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[Submitted] arm: Share a port for the two table walker objects
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
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[Submitted] arm: Remove unnecessary boot uncachability
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
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[Submitted] arm: remove the inline specifiers on the instruction constructors
|
ahansson
|
April 23rd, 2014, 12:12 p.m.
|
|
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[Submitted] arm: Remove the 'magic MSI register' in the GIC (PL390)
|
ahansson
|
March 6th, 2015, 1:39 p.m.
|
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[Submitted] arm: Relax ordering for some uncacheable accesses
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
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[Submitted] arm: Raise an alignment fault if a PC has illegal alignment
|
ahansson
|
December 12th, 2014, 5:45 p.m.
|
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[Submitted] arm: quick hack to allow a greater number of CPUs to a guest OS
|
ahansson
|
April 23rd, 2014, 12:16 p.m.
|
|
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[Submitted] arm: Panics in miscreg read functions can be tripped by O3 model
|
ahansson
|
April 23rd, 2014, 12:19 p.m.
|
|
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[Submitted] arm: Merge ISA files with pseudo instructions
|
ahansson
|
December 12th, 2014, 5:45 p.m.
|
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|
[Submitted] arm: Mark v7 cbz instructions as direct branches
|
ahansson
|
August 13th, 2014, 2:07 p.m.
|
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|
[Submitted] arm: Make sure UndefinedInstructions are properly initialized
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
|
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|
[Submitted] arm: Make memory ops work on 64bit/128-bit quantities
|
ahansson
|
August 13th, 2014, 2:08 p.m.
|
|
