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[Submitted] Mem: Separate the host and guest views of memory backing store
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ahansson
|
September 11th, 2012, 11:20 a.m.
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[Submitted] Mem: Add a maximum bandwidth to SimpleMemory
|
ahansson
|
September 12th, 2012, 9:38 a.m.
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[Submitted] scons: Use c++0x with gcc >= 4.4 instead of 4.6
|
ahansson
|
September 13th, 2012, 3:22 a.m.
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[Submitted] ruby: avoid using g_system_ptr for event scheduling
|
nilay
|
September 13th, 2012, 7:56 a.m.
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[Submitted] ruby: eliminate typedef integer_t
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nilay
|
September 13th, 2012, 7:57 a.m.
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[Submitted] ruby banked array: do away with event scheduling
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nilay
|
September 13th, 2012, 7:58 a.m.
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[Submitted] bus: removed outdated warn regarding 64 B block sizes
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atgutier
|
September 13th, 2012, 11:36 a.m.
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Models the request and response bandwidth between O3 and L1 (cache read and write ports)
|
aminfar
|
September 14th, 2012, 5:58 p.m.
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[Submitted] arm: Inst writing to "cntrlReg" registers not set as control inst
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npremill
|
September 19th, 2012, 12:33 p.m.
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[Submitted] Scons: Verbose messages when dependencies are not installed
|
ahansson
|
September 20th, 2012, 6:22 a.m.
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[Submitted] Mem: Tidy up bus member variables types
|
ahansson
|
September 20th, 2012, 6:39 a.m.
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[Submitted] Reset/dump ruby stats when m5 stats are reset/dumped.
|
lluc.alvarez
|
September 20th, 2012, 8:29 a.m.
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[Submitted] Ignore FUTEX_PRIVATE_FLAG of sys_futex in SE mode
|
lluc.alvarez
|
September 20th, 2012, 8:52 a.m.
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[Submitted] Mem: Use range operations in bus in preparation for striping
|
ahansson
|
September 21st, 2012, 9 a.m.
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[Submitted] Mem: Determine bus block size during initialisation
|
ahansson
|
September 21st, 2012, 9:03 a.m.
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[Submitted] Param: Fix proxy traversal to support chained proxies
|
ahansson
|
September 21st, 2012, 9:05 a.m.
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[Submitted] Clock: Inherit the clock from parent by default
|
ahansson
|
September 21st, 2012, 9:06 a.m.
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[Submitted] Regression: Set the clock for twosys-tsunami CPUs
|
ahansson
|
September 21st, 2012, 9:54 a.m.
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[Submitted] ruby: reset timing after cache warm up
|
nilay
|
September 24th, 2012, 5:52 p.m.
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[Submitted] ruby: move functional access to ruby system
|
nilay
|
September 24th, 2012, 5:55 p.m.
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[Submitted] ruby: remove some unused things in slicc
|
nilay
|
September 24th, 2012, 5:58 p.m.
|
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[Submitted] ruby: allow function definition in slicc structs
|
nilay
|
September 24th, 2012, 6:02 p.m.
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[Submitted] ruby: remove unused code in protocols
|
nilay
|
September 24th, 2012, 6:04 p.m.
|
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[Submitted] ruby: rename template_hack to template
|
nilay
|
September 24th, 2012, 6:06 p.m.
|
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[Submitted] ruby: changes to simple network
|
nilay
|
September 24th, 2012, 6:08 p.m.
|
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[Submitted] ruby: makes some members non-static
|
nilay
|
September 24th, 2012, 6:11 p.m.
|
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[Submitted] ruby: improved support for functional accesses
|
nilay
|
September 24th, 2012, 6:15 p.m.
|
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[Submitted] Configs: SE Script Fix for Alpha+Ruby Simulations.
|
musleh
|
September 25th, 2012, 11:40 a.m.
|
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[se] Initialize Linux' default code and data segments
|
vilanova
|
September 26th, 2012, 8:34 a.m.
|
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[Submitted] Regression: Use addTwoLevelCacheHierarchy in configs
|
ahansson
|
September 27th, 2012, 6:28 a.m.
|
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[Submitted] Regression: Use CPU clock and 32-byte width for L1-L2 bus
|
ahansson
|
September 27th, 2012, 6:30 a.m.
|
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[Submitted] Configs: Set the memtest clock to a reasonable value
|
ahansson
|
September 28th, 2012, 6:17 a.m.
|
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|
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[Submitted] Mem: Use cycles to express cache-related latencies
|
ahansson
|
September 28th, 2012, 7 a.m.
|
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|
|
Provide Python script command line options to set cache latencies
|
vilanova
|
September 28th, 2012, 8:52 a.m.
|
|
|
|
Let the user execute a file just before 'Simulation.run'
|
vilanova
|
September 28th, 2012, 8:55 a.m.
|
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[Submitted] Doxygen: Update the version of the Doxyfile
|
ahansson
|
September 28th, 2012, 9:56 a.m.
|
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[Submitted] sim: Fix as issue where exit events on instr queues are used after freed.
|
ali
|
October 1st, 2012, 3:07 p.m.
|
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[Submitted] ruby: remove AbstractMemOrCache
|
nilay
|
October 3rd, 2012, 9:03 p.m.
|
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[Submitted] ruby: register multiple memory controllers
|
nilay
|
October 3rd, 2012, 9:06 p.m.
|
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[Submitted] memtest: move check on outstanding requests
|
nilay
|
October 3rd, 2012, 9:10 p.m.
|
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|
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[Submitted] patch to fix early termination in SE multi-core simualtion
|
taozhang
|
October 5th, 2012, 3:45 p.m.
|
|
|
|
[Submitted] ARM: Set "uopSet_uop" as Conditional or Unconditional control
|
npremill
|
October 6th, 2012, 3:35 p.m.
|
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|
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[Discarded] Ruby: Add Ruby Stats Hit/Miss Profile Access for MESI/MOESI Protocols
|
musleh
|
October 7th, 2012, 12:58 p.m.
|
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[Submitted] Ruby: Add Ruby Stats Hit/Miss Profile Access for Protocols
|
musleh
|
October 7th, 2012, 4:59 p.m.
|
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[Submitted] Fix: Address a few minor issues identified by cppcheck
|
ahansson
|
October 12th, 2012, 1:38 a.m.
|
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[Submitted] Mem: Use deque instead of list for bus retries
|
ahansson
|
October 12th, 2012, 1:41 a.m.
|
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[Submitted] Checkpoint: Make system serialize call children
|
ahansson
|
October 12th, 2012, 1:46 a.m.
|
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[Submitted] cache: remove drainManager because it's not used
|
atgutier
|
October 16th, 2012, 9:47 a.m.
|
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|
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[Submitted] dev: Remove zero-time loop in DMA timing send
|
ahansson
|
October 19th, 2012, 2:29 a.m.
|
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[Discarded] gem5: Add the ability to create SimPoint BBV profiles
|
mhayenga
|
October 19th, 2012, 2:46 p.m.
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