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[Submitted] cpu: Add instruction opclass histogram to minor
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cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] base: Add total() to Vector2D stat
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cdunham
|
May 31st, 2016, 10:43 a.m.
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[Submitted] mem: Update DRAM configuration names
|
cdunham
|
January 17th, 2017, 10:04 p.m.
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[Submitted] mem: update DDR3 die revision
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cdunham
|
August 4th, 2016, 4:35 p.m.
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[Submitted] arm: Fix EL perceived at TLB for address translation instructions
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cdunham
|
June 21st, 2016, 1:41 p.m.
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[Discarded] multi-gem5: Simplify checkpoint support
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cdunham
|
September 21st, 2015, 6:59 p.m.
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[Discarded] arm, config: Fixups for the example big.LITTLE(tm) configuration
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cdunham
|
August 16th, 2016, 1:56 p.m.
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[Submitted] mem: Add initial HBM configurations
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cdunham
|
August 12th, 2015, 5:38 p.m.
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[Submitted] pseudo inst,util: Add an optional key parameter for the initparam pseudo instruction
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cdunham
|
November 19th, 2015, 5:44 p.m.
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[Submitted] sim: always generate sim/tags.cc
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cdunham
|
January 29th, 2016, 11:57 p.m.
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[Submitted] tests: check for gem5 binary before tests
|
cdunham
|
December 15th, 2016, 4:51 p.m.
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[Submitted] cpu: Fix LLSC atomic CPU wakeup
|
cdunham
|
February 9th, 2016, 9:29 p.m.
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[Submitted] sim: Fix clock_domain unserialization
|
cdunham
|
February 25th, 2016, 11:56 p.m.
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[Submitted] arm: Add TLBI instruction for stage 2 IPA's
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] probe: Add probe in Fetch, IEW, Rename and Commit
|
cdunham
|
August 11th, 2015, 9:05 p.m.
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[Submitted] pwr: Low-power idle power state for idle CPUs
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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[Submitted] multi-gem5: add support for multi gem5 runs
|
cdunham
|
May 15th, 2015, 10:18 p.m.
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[Submitted] cpu,isa,mem: Adds per-thread wakeup logic
|
cdunham
|
July 30th, 2015, 6:47 p.m.
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[Submitted] cpu: Add an indirect branch target predictor
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
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[Submitted] sim,kvm,arm: fix typos
|
cdunham
|
January 17th, 2017, 10:04 p.m.
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[Submitted] mem: Sort memory commands and update DRAMPower
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
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[Submitted] sim: Reuse the same limit_event in simulate()
|
cdunham
|
February 20th, 2015, 6:46 p.m.
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[Submitted] scons: remove dead leading underscore check
|
cdunham
|
June 8th, 2015, 11:35 p.m.
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[Submitted] arm: Add check to fault routing for hypervisor/virtualization
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] base: support gzip-compressed object files
|
cdunham
|
September 21st, 2015, 11:42 p.m.
|
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[Submitted] isa: Add parameter to pick different decoder inside ISA
|
cdunham
|
August 12th, 2015, 5:38 p.m.
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[Submitted] dist: Distributed Ethernet link support for distributed gem5 simulations
|
cdunham
|
November 19th, 2015, 5:44 p.m.
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[Submitted] arm: change instruction classes to catch hyp traps
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] sim: Add additional debug information when draining
|
cdunham
|
February 25th, 2016, 11:56 p.m.
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[Submitted] sim: make warning for absent optional parameters optional
|
cdunham
|
June 30th, 2015, 12:35 a.m.
|
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[Submitted] arm: correctly assign faulting IPA's to HPFAR_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] proto, probe: Add elastic trace probe to o3 cpu
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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[Submitted] sim: Add ability to break at specific kernel function
|
cdunham
|
September 30th, 2015, 9:42 p.m.
|
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[Submitted] mem, cpu: Add assertions to snoop invalidation logic
|
cdunham
|
February 11th, 2016, 12:31 a.m.
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[Submitted] sim: Adding support for power models
|
cdunham
|
March 5th, 2016, 12:21 a.m.
|
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[Submitted] arm: Change TLB software caching
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
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[Submitted] base: remove Trace::enabled flag
|
cdunham
|
August 31st, 2015, 6:35 p.m.
|
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[Submitted] cpu: Implement per-thread GHRs
|
cdunham
|
February 23rd, 2016, 8:58 p.m.
|
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[Submitted] sim, kvm: make KvmVM a System parameter
|
cdunham
|
January 17th, 2017, 10:04 p.m.
|
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[Submitted] mem: Modify drain to ensure banks and power are idled
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
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[Submitted] config: Add ability to exit simulation after initialization
|
cdunham
|
February 20th, 2015, 6:46 p.m.
|
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[Submitted] arm: Refactor aarch64 table walk logic to remove redundancy
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] cpu: Query CPU for inst executed from Python
|
cdunham
|
March 4th, 2016, 11:03 p.m.
|
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[Submitted] cpu: Change thread assignents for heterogenous SMT
|
cdunham
|
July 30th, 2015, 6:46 p.m.
|
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[Submitted] dist: Config file and parameter changes for distributed gem5 simulations
|
cdunham
|
November 19th, 2015, 5:44 p.m.
|
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|
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[Submitted] arm: invalidate TLB miscreg cache on modification of HSCTLR
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
|
|
[Discarded] multi-gem5: Add an optional key parameter for the initparam pseudo instruction.
|
cdunham
|
September 21st, 2015, 6:59 p.m.
|
|
|
|
[Submitted] misc: Add secondary dot output for DVFS domains
|
cdunham
|
February 25th, 2016, 11:56 p.m.
|
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|
|
[Submitted] sim: support checkpointing std::set<std::string>'s
|
cdunham
|
June 30th, 2015, 12:35 a.m.
|
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|
|
[Submitted] arm: Check TLB stage 2 permissions in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
|
