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[Submitted] dev: Set HDLCD default pixel clock for 1080p @ 60Hz
|
ahansson
|
April 23rd, 2014, 12:18 p.m.
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[Submitted] arm: quick hack to allow a greater number of CPUs to a guest OS
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ahansson
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April 23rd, 2014, 12:16 p.m.
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[Submitted] arm: Add Makefile for aarch64 build of util/m5
|
ahansson
|
April 23rd, 2014, 12:15 p.m.
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[Submitted] arch: remove inline specifiers on all inst constrs, all ISAs
|
ahansson
|
April 23rd, 2014, 12:14 p.m.
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[Submitted] arm: cleanup ARM ISA definition
|
ahansson
|
April 23rd, 2014, 12:13 p.m.
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[Submitted] arm: remove the inline specifiers on the instruction constructors
|
ahansson
|
April 23rd, 2014, 12:12 p.m.
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[Submitted] ext: disable PLY debugging
|
ahansson
|
April 23rd, 2014, 12:11 p.m.
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[Submitted] scons: remove vector typemaps obsoleted by SWIG 2.0.4
|
ahansson
|
April 23rd, 2014, 12:11 p.m.
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[Submitted] scons: update SCons SWIG version check to 2.0.4
|
ahansson
|
April 23rd, 2014, 12:10 p.m.
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[Discarded] arch: support dynamic ISA file generation in per-ISA SConscripts
|
ahansson
|
April 23rd, 2014, 12:23 p.m.
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[Discarded] arch: support dynamic ISA file generation in SConscripts
|
ahansson
|
April 23rd, 2014, 12:23 p.m.
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[Submitted] cpu: DRAM Traffic Generator
|
ahansson
|
March 7th, 2014, 11:37 p.m.
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[Submitted] mem: Add close adaptive paging policy to DRAM controller model
|
ahansson
|
March 7th, 2014, 11:44 p.m.
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[Submitted] mem: More descriptive address-mapping scheme names
|
ahansson
|
March 7th, 2014, 11:35 p.m.
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[Submitted] mem: DRAM controller tidying up
|
ahansson
|
March 7th, 2014, 11:43 p.m.
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[Submitted] mem: Change memory defaults to be more representative
|
ahansson
|
March 7th, 2014, 11:45 p.m.
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[Submitted] util: Add support for detection of gzipped packet traces
|
ahansson
|
March 12th, 2014, 10:58 a.m.
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|
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[Submitted] mem: Rename SimpleDRAM to a more suitable DRAMCtrl
|
ahansson
|
March 7th, 2014, 11:47 p.m.
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|
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[Submitted] mem: DDR3 config for comparing with DRAMSim2
|
ahansson
|
March 7th, 2014, 11:36 p.m.
|
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[Submitted] mem: Fix bug in DRAM bytes per activate
|
ahansson
|
March 7th, 2014, 11:42 p.m.
|
|
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[Submitted] mem: Limit the accesses to a page before forcing a precharge
|
ahansson
|
March 7th, 2014, 11:40 p.m.
|
|
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|
[Submitted] mem: Make DRAM write queue draining more aggressive
|
ahansson
|
March 7th, 2014, 11:39 p.m.
|
|
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|
[Submitted] config: Add a DRAM efficiency-sweep script
|
ahansson
|
March 7th, 2014, 11:38 p.m.
|
|
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|
[Submitted] ruby: Move Ruby debug flags to ruby dir and remove stale options
|
ahansson
|
March 16th, 2014, 12:55 p.m.
|
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|
[Submitted] mem: Track DRAM read/write switching and add hysteresis
|
ahansson
|
March 17th, 2014, 8:16 a.m.
|
|
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|
[Submitted] misc: Add panic_if / fatal_if / chatty_assert
|
ahansson
|
February 21st, 2014, 1:24 p.m.
|
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[Submitted] cpu: Make CPU and ThreadContext getters const
|
ahansson
|
March 6th, 2014, 7:22 p.m.
|
|
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|
[Submitted] mem: Fix incorrect assert failure in the Cache
|
ahansson
|
February 26th, 2014, 10:52 a.m.
|
|
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|
[Submitted] arm: Handle functional TLB walks properly
|
ahansson
|
February 26th, 2014, 10:53 a.m.
|
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|
[Submitted] mem: Wakeup sleeping CPUs without caches on LLSC
|
ahansson
|
February 21st, 2014, 1:21 p.m.
|
|
|
|
[Submitted] mem: Edit proto Packet and enhance the python script
|
ahansson
|
February 21st, 2014, 1:30 p.m.
|
|
|
|
[Discarded] ruby: Add bridges between RubyPort and NoncoherentBus
|
ahansson
|
January 23rd, 2014, 5:33 p.m.
|
|
|
|
[Submitted] ruby: Simplify RubyPort flow control and routing
|
ahansson
|
October 10th, 2013, 7:49 a.m.
|
|
|
|
[Submitted] dev: Include basic devices in NULL ISA build
|
ahansson
|
February 13th, 2014, 2:39 p.m.
|
|
|
|
[Submitted] mem: Filter cache snoops based on address ranges
|
ahansson
|
January 23rd, 2014, 8:23 a.m.
|
|
|
|
[Submitted] mem: Fix bug in PhysicalMemory use of mmap and munmap
|
ahansson
|
February 13th, 2014, 2:41 p.m.
|
|
|
|
[Submitted] cpu: Fix Checker register index use
|
ahansson
|
November 5th, 2013, 4:34 p.m.
|
|
|
|
[Submitted] mem: Add tRAS parameter to the DRAM controller model
|
ahansson
|
October 16th, 2013, 7:36 a.m.
|
|
|
|
[Submitted] mem: Schedule time for DRAM event taking tRAS into account
|
ahansson
|
October 16th, 2013, 7:38 a.m.
|
|
|
|
[Submitted] mem: Use the same timing calculation for DRAM read and write
|
ahansson
|
October 16th, 2013, 7:40 a.m.
|
|
|
|
[Submitted] mem: Pick the next DRAM request based on bank availability
|
ahansson
|
October 16th, 2013, 7:41 a.m.
|
|
|
|
[Submitted] mem: Make tXAW enforcement less conservative and per rank
|
ahansson
|
October 16th, 2013, 7:42 a.m.
|
|
|
|
[Submitted] mem: Less conservative tRAS in DRAM configurations
|
ahansson
|
October 16th, 2013, 7:43 a.m.
|
|
|
|
[Submitted] mem: Add tRRD as a timing parameter for the DRAM controller
|
ahansson
|
October 16th, 2013, 7:44 a.m.
|
|
|
|
[Submitted] mem: Just-in-time write scheduling in DRAM controller
|
ahansson
|
October 16th, 2013, 7:45 a.m.
|
|
|
|
[Submitted] mem: Add a simple adaptive version of the open-page policy
|
ahansson
|
October 16th, 2013, 7:47 a.m.
|
|
|
|
[Submitted] mem: Unify request selection for read and write queues
|
ahansson
|
October 16th, 2013, 7:48 a.m.
|
|
|
|
[Submitted] mem: Adding stats for DRAM power calculation
|
ahansson
|
October 16th, 2013, 7:49 a.m.
|
|
|
|
[Submitted] mem: Fix the LPDDR3 page size
|
ahansson
|
October 16th, 2013, 7:50 a.m.
|
|
|
|
[Submitted] sim: Clarify the difference between tracing and debugging
|
ahansson
|
October 17th, 2013, 5:37 p.m.
|
|
