|
|
[Submitted] MEM: Remove the otherPort from the cache ports
|
ahansson
|
January 18th, 2012, 2:33 a.m.
|
|
|
|
[Submitted] clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
|
ahansson
|
April 2nd, 2012, 12:41 p.m.
|
|
|
|
[Submitted] Port: Align port names in C++ and Python
|
ahansson
|
June 11th, 2012, 7:46 a.m.
|
|
|
|
[Submitted] Clock: Move the clock and related functions to ClockedObject
|
ahansson
|
July 11th, 2012, 1:56 a.m.
|
|
|
|
[Submitted] mem: Do not allocate space for packet data if not needed
|
ahansson
|
December 16th, 2015, 12:40 a.m.
|
|
|
|
[Submitted] AddrRange: Remove the unused range_ops header
|
ahansson
|
August 29th, 2012, 11:53 a.m.
|
|
|
|
[Submitted] Checkpoint: Pass maxtick to avoid undefined variable
|
ahansson
|
September 11th, 2012, 9:19 a.m.
|
|
|
|
[Submitted] Configs: Set the memtest clock to a reasonable value
|
ahansson
|
September 28th, 2012, 6:17 a.m.
|
|
|
|
stats: Implement code to manipulate vector2d stats in python
|
ahansson
|
January 15th, 2013, 10:25 a.m.
|
|
|
|
[Submitted] scons: Add warning for missing field initializers
|
ahansson
|
February 14th, 2013, 1:54 a.m.
|
|
|
|
[Submitted] mem: Adapt the LPDDR2 to match a single x32 channel
|
ahansson
|
April 22nd, 2013, 2:45 p.m.
|
|
|
|
[Submitted] arm: quick hack to allow a greater number of CPUs to a guest OS
|
ahansson
|
April 23rd, 2014, 12:16 p.m.
|
|
|
|
[Submitted] mem: Simplify DRAM response scheduling
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] arm: Make memory ops work on 64bit/128-bit quantities
|
ahansson
|
August 13th, 2014, 2:08 p.m.
|
|
|
|
[Submitted] cpu: use probes infrastructure to do simpoint profiling
|
ahansson
|
September 10th, 2014, 7:51 a.m.
|
|
|
|
[Submitted] mem: Dynamically determine page bytes in memory components
|
ahansson
|
September 29th, 2014, 10:39 a.m.
|
|
|
|
[Submitted] arch: Make readMiscRegNoEffect const throughout
|
ahansson
|
February 3rd, 2015, 7:57 p.m.
|
|
|
|
[Submitted] tests: Run regression timeout as foreground
|
ahansson
|
February 19th, 2015, 7:55 a.m.
|
|
|
|
[Submitted] arm: Relax ordering for some uncacheable accesses
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
|
|
[Submitted] MEM: Remove the notion of the default port
|
ahansson
|
December 19th, 2011, 5:56 a.m.
|
|
|
|
[Submitted] Ruby: Change the access permissions for MOESI hammer
|
ahansson
|
January 10th, 2012, 9:18 a.m.
|
|
|
|
[Submitted] mem: Remove extraneous acquire/release flags and attributes
|
ahansson
|
August 5th, 2015, 8:51 a.m.
|
|
|
|
[Submitted] mem: Only track snooping ports in the snoop filter
|
ahansson
|
August 21st, 2015, 3:50 p.m.
|
|
|
|
[Discarded] Cache: Remove redundant check for uncacheable snoops
|
ahansson
|
May 18th, 2012, 9:12 a.m.
|
|
|
|
[Submitted] DMA: Refactor the DMA device and align timing and atomic
|
ahansson
|
July 21st, 2012, 7:19 a.m.
|
|
|
|
[Discarded] mem: Adopt a more sensible cache class hierarchy
|
ahansson
|
February 24th, 2016, 9:29 a.m.
|
|
|
|
[Submitted] Fix: Address a few minor issues identified by cppcheck
|
ahansson
|
October 12th, 2012, 1:38 a.m.
|
|
|
|
[Submitted] mem: Skip address mapper range checks to allow more flexibility
|
ahansson
|
December 6th, 2012, 8:02 p.m.
|
|
|
|
[Submitted] mem: SimpleDRAM variable naming and whitespace fixes
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Add optional request flags to the packet trace
|
ahansson
|
March 14th, 2013, 7 a.m.
|
|
|
|
[Submitted] mem: Add basic stats to the buses
|
ahansson
|
April 5th, 2013, 6:39 a.m.
|
|
|
|
[Submitted] cpu: Prune the stale TraceCPU
|
ahansson
|
April 27th, 2013, 12:17 p.m.
|
|
|
|
[Submitted] mem: Allow disabling of tXAW through a 0 activation limit
|
ahansson
|
July 12th, 2013, 9:46 a.m.
|
|
|
|
[Submitted] arch: Resurrect the NOISA build target and rename it NULL
|
ahansson
|
August 19th, 2013, 9:42 a.m.
|
|
|
|
[Submitted] mem: Just-in-time write scheduling in DRAM controller
|
ahansson
|
October 16th, 2013, 7:45 a.m.
|
|
|
|
[Submitted] mem: Filter cache snoops based on address ranges
|
ahansson
|
January 23rd, 2014, 8:23 a.m.
|
|
|
|
[Discarded] arch: support dynamic ISA file generation in per-ISA SConscripts
|
ahansson
|
April 23rd, 2014, 12:23 p.m.
|
|
|
|
[Submitted] config: Refactor RealviewEMM to fit into new config system
|
ahansson
|
August 20th, 2014, 8:34 a.m.
|
|
|
|
[Submitted] mem: Add DDR4 bank group timing
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] mem: Add DRAMPower wrapping class
|
ahansson
|
September 29th, 2014, 10:42 a.m.
|
|
|
|
[Submitted] mem: Assume all dynamic packet data is array allocated
|
ahansson
|
November 17th, 2014, 6:14 a.m.
|
|
|
|
[Submitted] arm: Add support for filtering in the PMU
|
ahansson
|
December 12th, 2014, 5:44 p.m.
|
|
|
|
[Submitted] mem: Remove Packet source from ForwardResponseRecord
|
ahansson
|
January 12th, 2015, 4:09 p.m.
|
|
|
|
[Submitted] mem: Clarification of packet crossbar timings
|
ahansson
|
February 5th, 2015, 12:52 p.m.
|
|
|
|
[Submitted] dev: Add support for i2c devices
|
ahansson
|
March 18th, 2015, 4:41 p.m.
|
|
|
|
[Submitted] MEM: Differentiate functional cache accesses from CPU and memory
|
ahansson
|
January 5th, 2012, 5:17 a.m.
|
|
|
|
[Submitted] mem: Add ReadCleanReq and ReadSharedReq packets
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
|
|
[Submitted] MEM: Fatal when no port can be found for an address
|
ahansson
|
February 12th, 2012, 10:22 a.m.
|
|
|
|
[Submitted] mem: Remove unused RequestCause in cache
|
ahansson
|
July 13th, 2015, 3:17 p.m.
|
|
|
|
[Submitted] CPU: Check that the interrupt controller is created when needed
|
ahansson
|
March 2nd, 2012, 4:45 a.m.
|
|
