Review Board 2.0.15


All Review Requests

Summary
Submitter
Posted Last Updated
MEM: Do not forward uncacheable to bus snoopers
ahansson
May 4th, 2012, 9:47 a.m.
mem: Do not alter cache block state on uncacheable snoops
ahansson
December 9th, 2015, 11:57 p.m.
mem: Do not allocate space for packet data if not needed
ahansson
December 16th, 2015, 12:40 a.m.
MEM: Differentiate functional cache accesses from CPU and memory
ahansson
January 5th, 2012, 5:17 a.m.
Mem: Determine bus block size during initialisation
ahansson
September 21st, 2012, 9:03 a.m.
mem: Delay responses in the crossbar before forwarding
ahansson
June 15th, 2015, 6:06 p.m.
mem: Deduce if cache should forward snoops
ahansson
December 28th, 2015, 6:14 p.m.
mem: Deallocate all write-queue entries when sent
ahansson
April 20th, 2016, 5:18 p.m.
mem: DDR3 config for comparing with DRAMSim2
ahansson
March 7th, 2014, 11:36 p.m.
mem: Cycles converted to Ticks in atomic cache accesses
ahansson
May 23rd, 2013, 12:47 a.m.
mem: Create a separate class for the cache write buffer
ahansson
February 24th, 2016, 9:28 a.m.
mem: Create a request copy for deferred snoops
ahansson
April 2nd, 2015, 9:31 a.m.
mem: Convert Request static const flags to enums
ahansson
June 26th, 2015, 9:26 p.m.
mem: Cleanup Packet::checkFunctional and hasData usage
ahansson
November 17th, 2014, 6:16 a.m.
[Discarded] mem: Cleanup packet attributes and rely on command type
ahansson
August 6th, 2015, 9:41 p.m.
mem: Cleanup flow for uncacheable accesses
ahansson
March 17th, 2015, 7:10 p.m.
MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
ahansson
January 29th, 2012, 10:49 a.m.
mem: Clean up Request initialisation
ahansson
January 5th, 2015, 4:35 p.m.
mem: Clean up packet data allocation
ahansson
November 17th, 2014, 6:17 a.m.
mem: Clarify usage of latency in the cache
ahansson
February 5th, 2015, 12:52 p.m.
mem: Clarify express snoop behaviour
ahansson
January 26th, 2015, 6:23 p.m.
mem: Clarify cache MSHR handling on fill
ahansson
October 13th, 2015, 3:35 p.m.
mem: Clarify cache behaviour for pending dirty responses
ahansson
January 26th, 2015, 6:23 p.m.
mem: Clarification of packet crossbar timings
ahansson
February 5th, 2015, 12:52 p.m.
[Discarded] MEM: Changes for SETranslatingProxy integration into Ruby
ahansson
November 28th, 2011, 10:19 a.m.
mem: Change prefetcher to use random_mt
ahansson
December 12th, 2014, 5:50 p.m.
mem: Change memory defaults to be more representative
ahansson
March 7th, 2014, 11:45 p.m.
mem: Change accessor function names to match the port interface
ahansson
February 14th, 2013, 1:53 a.m.
mem: Change AbstractMemory defaults to match the common case
ahansson
July 19th, 2013, 8:33 a.m.
mem: Cancel cache retry event when blocking port
ahansson
March 14th, 2013, 7:04 a.m.
mem: Be less conservative in clearing load locks in the cache
ahansson
January 21st, 2016, 6:12 p.m.
mem: Avoid setting markPending if not needed
ahansson
August 31st, 2015, 9:20 a.m.
mem: Avoid explicitly zeroing the memory backing store
ahansson
April 22nd, 2013, 2:44 p.m.
mem: Avoid DRAM write queue iteration for merging and read lookup
ahansson
April 24th, 2015, 4:32 p.m.
mem: Auto-generate CommMonitor trace file names
ahansson
April 23rd, 2014, 12:19 p.m.
mem: Assume all dynamic packet data is array allocated
ahansson
November 17th, 2014, 6:14 a.m.
mem: Always use SenderState for response routing in RubyPort
ahansson
January 5th, 2015, 4:50 p.m.
mem: Allow read-only caches and check compliance
ahansson
June 10th, 2015, 7:59 a.m.
mem: Allow disabling of tXAW through a 0 activation limit
ahansson
July 12th, 2013, 9:46 a.m.
mem: Allocate cache writebacks before new MSHRs
ahansson
March 22nd, 2015, 7:35 a.m.
[Discarded] mem: Align rules for sinking packets at the slave
ahansson
October 26th, 2015, 6:14 p.m.
mem: Align how snoops are handled when hitting writebacks
ahansson
December 30th, 2015, 7:11 p.m.
mem: Align downstream cache packet creation in atomic and timing
ahansson
March 31st, 2016, 6:21 p.m.
mem: Align cache timing to clock edges
ahansson
June 4th, 2013, 10:46 a.m.
mem: Align cache behaviour in atomic when upstream is responding
ahansson
January 1st, 2016, 2:16 p.m.
mem: Align all MSHR entries to block boundaries
ahansson
March 17th, 2015, 7:09 p.m.
[Discarded] mem: Adopt a more sensible cache class hierarchy
ahansson
February 24th, 2016, 9:29 a.m.
mem: Adjust cache queue reserve to more conservative values
ahansson
February 24th, 2016, 9:28 a.m.
mem: Address mapping with fine-grained channel interleaving
ahansson
March 28th, 2013, 3:28 a.m.
mem: Adding verbose debug output in the memory system
ahansson
March 14th, 2013, 7:05 a.m.
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