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[Submitted] mem: Schedule time for DRAM event taking tRAS into account
|
ahansson
|
October 16th, 2013, 7:38 a.m.
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[Submitted] mem: Add tRAS parameter to the DRAM controller model
|
ahansson
|
October 16th, 2013, 7:36 a.m.
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[Submitted] ruby: Simplify RubyPort flow control and routing
|
ahansson
|
October 10th, 2013, 7:49 a.m.
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[Submitted] ext: Fix fputils compiler flags to ensure ISO C99
|
ahansson
|
October 1st, 2013, 8:58 a.m.
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[Submitted] kvm: Only include KVM support for supported kernels
|
ahansson
|
September 30th, 2013, 5:34 p.m.
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[Submitted] swig: Warn on use of incompatible swig/gcc combinations
|
ahansson
|
September 6th, 2013, 9:59 a.m.
|
|
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[Submitted] swig: Fix issue with circular import in 2.0.9/2.0.10
|
ahansson
|
September 6th, 2013, 7:22 a.m.
|
|
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[Submitted] tests: Move ISA-independent tests to the NULL ISA
|
ahansson
|
August 19th, 2013, 9:43 a.m.
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|
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[Submitted] arch: Resurrect the NOISA build target and rename it NULL
|
ahansson
|
August 19th, 2013, 9:42 a.m.
|
|
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[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (2/2)
|
ahansson
|
August 19th, 2013, 9:41 a.m.
|
|
|
|
[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (1/2)
|
ahansson
|
August 19th, 2013, 9:39 a.m.
|
|
|
|
[Submitted] cpu: Move the branch predictor out of the BaseCPU
|
ahansson
|
August 19th, 2013, 9:38 a.m.
|
|
|
|
[Submitted] arch: Header clean up for NOISA resurrection
|
ahansson
|
August 19th, 2013, 9:38 a.m.
|
|
|
|
[Submitted] alpha: Move system virtProxy to Alpha only
|
ahansson
|
August 19th, 2013, 9:34 a.m.
|
|
|
|
[Submitted] util: Add ini string as tooltip info in dot output
|
ahansson
|
August 19th, 2013, 9:33 a.m.
|
|
|
|
[Submitted] util: Add colours to the dot output
|
ahansson
|
August 19th, 2013, 9:33 a.m.
|
|
|
|
[Submitted] util: Add class name to dot graph and output to svg
|
ahansson
|
August 19th, 2013, 9:32 a.m.
|
|
|
|
[Submitted] scons: Enable build on OSX
|
ahansson
|
August 19th, 2013, 9:30 a.m.
|
|
|
|
[Submitted] cpu: Fix timing CPU drain check
|
ahansson
|
August 18th, 2013, 3:35 p.m.
|
|
|
|
[Submitted] cpu: Fix a bug in the O3 CPU introduced by the cache line patch
|
ahansson
|
August 7th, 2013, 3:12 p.m.
|
|
|
|
[Submitted] mem: Perform write merging in the DRAM write queue
|
ahansson
|
August 5th, 2013, 4:55 p.m.
|
|
|
|
[Submitted] alpha: Check interrupts before quiesce
|
ahansson
|
August 5th, 2013, 8:35 a.m.
|
|
|
|
[Submitted] config: Command line support for multi-channel memory
|
ahansson
|
July 19th, 2013, 8:35 a.m.
|
|
|
|
[Submitted] mem: Change AbstractMemory defaults to match the common case
|
ahansson
|
July 19th, 2013, 8:33 a.m.
|
|
|
|
[Submitted] cpu: Fix TrafficGen trace playback
|
ahansson
|
July 18th, 2013, 1:17 p.m.
|
|
|
|
[Submitted] mem: Use STL deque in favour of list for DRAM queues
|
ahansson
|
July 18th, 2013, 12:59 p.m.
|
|
|
|
[Submitted] stats: Fix issue when printing 2D vectors
|
ahansson
|
July 16th, 2013, 7:44 a.m.
|
|
|
|
[Submitted] config: Move the memory instantiation outside FSConfig
|
ahansson
|
July 15th, 2013, 8:42 a.m.
|
|
|
|
[Submitted] config: Update script to set cache line size on system
|
ahansson
|
July 12th, 2013, 3:07 p.m.
|
|
|
|
[Submitted] mem: Set the cache line size on a system level
|
ahansson
|
July 12th, 2013, 3:06 p.m.
|
|
|
|
[Submitted] mem: Add an internal packet queue in SimpleMemory
|
ahansson
|
July 12th, 2013, 2:04 p.m.
|
|
|
|
[Submitted] mem: Allow disabling of tXAW through a 0 activation limit
|
ahansson
|
July 12th, 2013, 9:46 a.m.
|
|
|
|
[Submitted] sim: Make MaxTick in Python match the one in C++
|
ahansson
|
July 12th, 2013, 9:41 a.m.
|
|
|
|
[Discarded] config: Change default memory size to 256 MB
|
ahansson
|
July 5th, 2013, 1:18 p.m.
|
|
|
|
[Discarded] scons: Move the warning about self assignment to SWIG code only
|
ahansson
|
June 28th, 2013, 10:34 a.m.
|
|
|
|
[Submitted] power: Add voltage domains to the clock domains
|
ahansson
|
June 27th, 2013, 4:40 p.m.
|
|
|
|
[Submitted] scons: Use python-config instead of distutils
|
ahansson
|
June 26th, 2013, 5:35 p.m.
|
|
|
|
[Submitted] mem: Reorganize cache tags and make them a SimObject
|
ahansson
|
June 20th, 2013, 5:47 p.m.
|
|
|
|
[Submitted] config: Remove Clock parameter multiplication
|
ahansson
|
June 11th, 2013, 9:31 a.m.
|
|
|
|
[Discarded] config: Use BaseSESystem in multi-processor regressions
|
ahansson
|
June 6th, 2013, 2:32 p.m.
|
|
|
|
[Submitted] config: Add a BaseSESystem builder for re-use in regressions
|
ahansson
|
June 6th, 2013, 2:30 p.m.
|
|
|
|
[Submitted] tests: Prune 00.gzip from the regressions
|
ahansson
|
June 6th, 2013, 2:28 p.m.
|
|
|
|
[Submitted] mem: Tidy up the bridge with const and additional checks
|
ahansson
|
June 4th, 2013, 10:49 a.m.
|
|
|
|
[Submitted] mem: Fix CommMonitor style and response check
|
ahansson
|
June 4th, 2013, 10:47 a.m.
|
|
|
|
[Submitted] mem: Align cache timing to clock edges
|
ahansson
|
June 4th, 2013, 10:46 a.m.
|
|
|
|
[Submitted] cpu: Consider instructions waiting for FU completion in draining
|
ahansson
|
June 4th, 2013, 10:01 a.m.
|
|
|
|
[Discarded] sim: Pre-compute the clock period
|
ahansson
|
May 27th, 2013, 11:25 a.m.
|
|
|
|
[Submitted] sim: Add the notion of clock domains to all ClockedObjects
|
ahansson
|
May 24th, 2013, 3:32 a.m.
|
|
|
|
[Submitted] config: Rename clock option to Ruby clock
|
ahansson
|
May 24th, 2013, 3:30 a.m.
|
|
|
|
[Submitted] config: Add a system clock command-line option
|
ahansson
|
May 24th, 2013, 3:28 a.m.
|
|
