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[Submitted] mem: Add a WideIO DRAM configuration
|
ahansson
|
March 28th, 2013, 3:27 a.m.
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[Submitted] config: Add a mem-type config option to se/fs scripts
|
ahansson
|
March 28th, 2013, 3:28 a.m.
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[Submitted] cpu: Make the generators usable outside the TrafficGen module
|
ahansson
|
March 28th, 2013, 3:28 a.m.
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[Submitted] cpu: Use request flags in trace playback
|
ahansson
|
March 28th, 2013, 3:28 a.m.
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[Submitted] mem: More descriptive enum names for address mapping
|
ahansson
|
March 28th, 2013, 3:28 a.m.
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[Submitted] mem: Address mapping with fine-grained channel interleaving
|
ahansson
|
March 28th, 2013, 3:28 a.m.
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[Submitted] mem: Add basic stats to the buses
|
ahansson
|
April 5th, 2013, 6:39 a.m.
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[Submitted] base: Avoid size limitation on protobuf coded streams
|
ahansson
|
April 22nd, 2013, 2:43 p.m.
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[Submitted] util: Auto generate the packet proto definitions
|
ahansson
|
April 22nd, 2013, 2:44 p.m.
|
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[Submitted] mem: Avoid explicitly zeroing the memory backing store
|
ahansson
|
April 22nd, 2013, 2:44 p.m.
|
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[Submitted] mem: Adapt the LPDDR2 to match a single x32 channel
|
ahansson
|
April 22nd, 2013, 2:45 p.m.
|
|
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[Submitted] mem: Add a LPDDR3-1600 configuration
|
ahansson
|
April 22nd, 2013, 2:45 p.m.
|
|
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[Submitted] mem: Tidy up a few variables in the bus
|
ahansson
|
April 22nd, 2013, 3:32 p.m.
|
|
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[Submitted] mem: Separate the two snoop response cases in the bus
|
ahansson
|
April 22nd, 2013, 3:34 p.m.
|
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[Submitted] mem: Make the buses multi layered
|
ahansson
|
April 22nd, 2013, 3:35 p.m.
|
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[Submitted] mem: Make returning snoop responses occupy response layer
|
ahansson
|
April 22nd, 2013, 3:37 p.m.
|
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[Submitted] cpu: Fold together the StateGraph and the TrafficGen
|
ahansson
|
April 23rd, 2013, 12:25 a.m.
|
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[Submitted] cpu: Move traffic generator sending out of generator states
|
ahansson
|
April 23rd, 2013, 12:26 a.m.
|
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[Submitted] cpu: Block traffic generator when requests have to retry
|
ahansson
|
April 23rd, 2013, 12:29 a.m.
|
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[Submitted] cpu: Add request elasticity to the traffic generator
|
ahansson
|
April 23rd, 2013, 12:32 a.m.
|
|
|
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[Submitted] cpu: Prune the stale TraceCPU
|
ahansson
|
April 27th, 2013, 12:17 p.m.
|
|
|
|
[Submitted] mem: Spring cleaning of MSHR and MSHRQueue
|
ahansson
|
May 9th, 2013, 3:18 a.m.
|
|
|
|
[Submitted] mem: Add static latency to the DRAM controller
|
ahansson
|
May 11th, 2013, 10:28 a.m.
|
|
|
|
[Submitted] mem: Add bytes per activate DRAM controller stat
|
ahansson
|
May 11th, 2013, 10:29 a.m.
|
|
|
|
[Submitted] mem: More descriptive DRAM config names
|
ahansson
|
May 14th, 2013, 12:45 a.m.
|
|
|
|
[Submitted] mem: Remove the cache builder
|
ahansson
|
May 23rd, 2013, 12:44 a.m.
|
|
|
|
[Submitted] scons: Identify runs that fail and runs with stats differences
|
ahansson
|
May 23rd, 2013, 12:45 a.m.
|
|
|
|
[Submitted] mem: Cycles converted to Ticks in atomic cache accesses
|
ahansson
|
May 23rd, 2013, 12:47 a.m.
|
|
|
|
[Submitted] config: Remove redundant default clocks
|
ahansson
|
May 23rd, 2013, 12:50 a.m.
|
|
|
|
[Submitted] config: Add a CPU clock command-line option
|
ahansson
|
May 24th, 2013, 3:18 a.m.
|
|
|
|
[Submitted] config: Add a system clock command-line option
|
ahansson
|
May 24th, 2013, 3:28 a.m.
|
|
|
|
[Submitted] config: Rename clock option to Ruby clock
|
ahansson
|
May 24th, 2013, 3:30 a.m.
|
|
|
|
[Submitted] sim: Add the notion of clock domains to all ClockedObjects
|
ahansson
|
May 24th, 2013, 3:32 a.m.
|
|
|
|
[Discarded] sim: Pre-compute the clock period
|
ahansson
|
May 27th, 2013, 11:25 a.m.
|
|
|
|
[Submitted] cpu: Consider instructions waiting for FU completion in draining
|
ahansson
|
June 4th, 2013, 10:01 a.m.
|
|
|
|
[Submitted] mem: Align cache timing to clock edges
|
ahansson
|
June 4th, 2013, 10:46 a.m.
|
|
|
|
[Submitted] mem: Fix CommMonitor style and response check
|
ahansson
|
June 4th, 2013, 10:47 a.m.
|
|
|
|
[Submitted] mem: Tidy up the bridge with const and additional checks
|
ahansson
|
June 4th, 2013, 10:49 a.m.
|
|
|
|
[Submitted] tests: Prune 00.gzip from the regressions
|
ahansson
|
June 6th, 2013, 2:28 p.m.
|
|
|
|
[Submitted] config: Add a BaseSESystem builder for re-use in regressions
|
ahansson
|
June 6th, 2013, 2:30 p.m.
|
|
|
|
[Discarded] config: Use BaseSESystem in multi-processor regressions
|
ahansson
|
June 6th, 2013, 2:32 p.m.
|
|
|
|
[Submitted] config: Remove Clock parameter multiplication
|
ahansson
|
June 11th, 2013, 9:31 a.m.
|
|
|
|
[Submitted] mem: Reorganize cache tags and make them a SimObject
|
ahansson
|
June 20th, 2013, 5:47 p.m.
|
|
|
|
[Submitted] scons: Use python-config instead of distutils
|
ahansson
|
June 26th, 2013, 5:35 p.m.
|
|
|
|
[Submitted] power: Add voltage domains to the clock domains
|
ahansson
|
June 27th, 2013, 4:40 p.m.
|
|
|
|
[Discarded] scons: Move the warning about self assignment to SWIG code only
|
ahansson
|
June 28th, 2013, 10:34 a.m.
|
|
|
|
[Discarded] config: Change default memory size to 256 MB
|
ahansson
|
July 5th, 2013, 1:18 p.m.
|
|
|
|
[Submitted] sim: Make MaxTick in Python match the one in C++
|
ahansson
|
July 12th, 2013, 9:41 a.m.
|
|
|
|
[Submitted] mem: Allow disabling of tXAW through a 0 activation limit
|
ahansson
|
July 12th, 2013, 9:46 a.m.
|
|
|
|
[Submitted] mem: Add an internal packet queue in SimpleMemory
|
ahansson
|
July 12th, 2013, 2:04 p.m.
|
|
