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[se] Initialize Linux' default code and data segments
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vilanova
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September 26th, 2012, 8:34 a.m.
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Config: Instantiate Interrupt Controller for run.py
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musleh
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December 30th, 2012, 8:22 p.m.
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switching memleak
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lukefahr
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July 2nd, 2012, 9:34 a.m.
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cpu: profileEvent access code is modified to be executed only when FullSystem is on
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drh5
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January 14th, 2013, 8:29 a.m.
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ruby: ruby tester support for separate instr and data ports
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drh5
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January 14th, 2013, 8:26 a.m.
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slicc: generate inport logic in separate functions
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drh5
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January 14th, 2013, 8:28 a.m.
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slicc: added generic mach to mach function
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drh5
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January 14th, 2013, 8:26 a.m.
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ruby: Atomic Message Interface Support
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drh5
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January 14th, 2013, 8:28 a.m.
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x86: Fix SMT support (zeroReg, TLBs)
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apellegr
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June 29th, 2012, 3:15 p.m.
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Models the request and response bandwidth between O3 and L1 (cache read and write ports)
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aminfar
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September 14th, 2012, 5:58 p.m.
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stats: Add example script to extract stats from SQL database
|
ahansson
|
January 15th, 2013, 10:27 a.m.
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stats: Add length of all stats to the SQL stats table
|
ahansson
|
January 15th, 2013, 10:33 a.m.
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stats: Optimise SQL stats output to improve speed and file size
|
ahansson
|
January 15th, 2013, 10:32 a.m.
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stats: Add version information and timestamp to the SQL database
|
ahansson
|
January 15th, 2013, 10:36 a.m.
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stats: Add the geometric mean to the histogram
|
ahansson
|
January 15th, 2013, 10:29 a.m.
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stats: Add sparse histogram to python stats
|
ahansson
|
January 15th, 2013, 10:28 a.m.
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stats: Implement code to manipulate vector2d stats in python
|
ahansson
|
January 15th, 2013, 10:25 a.m.
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stats: Store vector stats using doubles and compress with zlib
|
ahansson
|
January 15th, 2013, 10:34 a.m.
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cpu: Remove incorrect branch predictor drain checks
|
andysan
|
February 7th, 2013, 3:27 a.m.
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Let the user execute a file just before 'Simulation.run'
|
vilanova
|
September 28th, 2012, 8:55 a.m.
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Ruby: Add Flushing Support to MOESI CMP directory Protocol
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musleh
|
December 2nd, 2012, 5:32 p.m.
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stats: Add documentation to the python statistics system
|
ahansson
|
January 15th, 2013, 10:24 a.m.
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stats: Add total calculation to python formula class
|
ahansson
|
January 29th, 2013, 2:20 a.m.
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stats: Fix some bugs in the python based stats system
|
ahansson
|
January 29th, 2013, 2:17 a.m.
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stats: Add the total for vector and formula stats to SQL output
|
ahansson
|
January 15th, 2013, 10:30 a.m.
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stats: Optimise the text-based stats output to improve speed
|
ahansson
|
January 15th, 2013, 10:31 a.m.
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stats: Add a separate display class for vector formulas
|
ahansson
|
January 29th, 2013, 2:24 a.m.
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stats: Add SQLite database as an output format
|
ahansson
|
January 15th, 2013, 10:26 a.m.
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ruby: rename wakeUpBuffer Function
|
musleh
|
May 18th, 2013, 1:52 p.m.
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cpu: Limit the size of the decode cache
|
andysan
|
June 3rd, 2013, 5:29 a.m.
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sim: unify memory & ethernet port binding mechanisms.
|
stever
|
June 13th, 2013, 7:46 a.m.
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Fixed an LSQ full check condition at rename.
|
yxw0985
|
May 13th, 2011, 2:29 p.m.
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cpu: discard nops at decode in o3
|
mhayenga
|
March 29th, 2013, 7:27 p.m.
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arm: mark IT instructions as nops
|
mhayenga
|
March 29th, 2013, 7:41 p.m.
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Add Global-Global (gAG) branch predictor
|
taylorlloyd
|
May 10th, 2013, 10:18 a.m.
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mem: add a knob to turn on/off bank blocking model
|
rioshering
|
April 15th, 2013, 11:54 a.m.
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mem: add retry mechanism for cache fills in classic cache model
|
rioshering
|
April 17th, 2013, 11:18 a.m.
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x86: Implementation of Int3 and Int_Ib in long mode
|
stever
|
August 28th, 2013, 3:52 a.m.
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gem5ops: Update util/m5/Makefile.x86 to compile Java JNI for gem5Ops
|
gedare
|
November 11th, 2013, 9:50 p.m.
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O3CPU: Revive cachePorts per-cycle dcache access limit
|
erik.t
|
May 17th, 2013, 3:53 a.m.
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sim: eventq: Initialize _curEventQueue to dummy queue
|
olajep
|
December 28th, 2013, 7:32 p.m.
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o3: Fix starvation issue in Round Robin SMT commit policy
|
sleimanf
|
March 4th, 2014, 10 p.m.
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mem: model data array bank in classic cache
|
rioshering
|
March 31st, 2013, 3:47 p.m.
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ruby: cluster topology config fix
|
musleh
|
April 10th, 2014, 2:31 a.m.
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cache: enable multiple stores per cycle
|
stever
|
May 14th, 2014, 5:46 a.m.
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o3: issue excl. prefetch as soon as store address is available
|
stever
|
May 14th, 2014, 5:47 a.m.
|
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sim: stopgap for race-conditions when using multiple EventQueues
|
mbrown
|
August 1st, 2014, 5:54 p.m.
|
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Adding TSX support to gem5
|
pradip16
|
July 5th, 2014, 3:10 a.m.
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config, x86: add ethernet support for x86 fullsystem
|
majiuyue
|
June 13th, 2014, 9:23 a.m.
|
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sim: Add a KvmVM parameter to the base system object.
|
gblack
|
November 23rd, 2014, 11:03 a.m.
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