|
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[Submitted] MEM: Separate queries for snooping and address ranges
|
ahansson
|
December 19th, 2011, 5:58 a.m.
|
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|
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[Submitted] MEM: Separate requests and responses for timing accesses
|
ahansson
|
April 11th, 2012, 8:23 a.m.
|
|
|
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[Submitted] MEM: Separate snoops and normal memory requests/responses
|
ahansson
|
April 2nd, 2012, 6:49 a.m.
|
|
|
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[Submitted] Mem: Separate the host and guest views of memory backing store
|
ahansson
|
September 11th, 2012, 11:20 a.m.
|
|
|
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[Submitted] mem: Separate the two snoop response cases in the bus
|
ahansson
|
April 22nd, 2013, 3:34 p.m.
|
|
|
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[Submitted] mem: Separate waiting for the bus and waiting for a peer
|
ahansson
|
March 14th, 2013, 7:02 a.m.
|
|
|
|
[Submitted] mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv
|
nnikoleris
|
November 18th, 2016, 2:53 p.m.
|
|
|
|
[Submitted] mem: Set the cache line size on a system level
|
ahansson
|
July 12th, 2013, 3:06 p.m.
|
|
|
|
[Submitted] mem: Simple Snoop Filter
|
ahansson
|
September 10th, 2014, 7:53 a.m.
|
|
|
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[Submitted] mem: SimpleDRAM variable naming and whitespace fixes
|
ahansson
|
February 19th, 2013, 6:38 a.m.
|
|
|
|
[Submitted] mem: Simplify cache packet handling for uncacheable writes
|
ahansson
|
March 31st, 2016, 6:19 p.m.
|
|
|
|
[Submitted] MEM: Simplify cache ports preparing for master/slave split
|
ahansson
|
February 21st, 2012, 3:21 a.m.
|
|
|
|
[Submitted] mem: Simplify DRAM response scheduling
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] mem: Simplify page close checks for adaptive policies
|
rizwanab
|
April 9th, 2015, 8:46 p.m.
|
|
|
|
[Submitted] MEM: Simplify ports by removing EventManager
|
ahansson
|
December 19th, 2011, 5:55 a.m.
|
|
|
|
[Submitted] mem: Skip address mapper range checks to allow more flexibility
|
ahansson
|
December 6th, 2012, 8:02 p.m.
|
|
|
|
[Submitted] mem: Snoop into caches on uncacheable accesses
|
ahansson
|
March 30th, 2015, 9:17 a.m.
|
|
|
|
[Submitted] mem: Sort memory commands and update DRAMPower
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: Split port retry for all different packet classes
|
ahansson
|
February 7th, 2015, 5:24 p.m.
|
|
|
|
[Submitted] MEM: Split SimpleTimingPort into PacketQueue and ports
|
ahansson
|
February 27th, 2012, 2:29 a.m.
|
|
|
|
[Submitted] mem: Split the hit_latency into tag_latency and data_latency
|
senni
|
June 15th, 2016, 2:26 p.m.
|
|
|
|
[Submitted] mem: Split WriteInvalidateReq into write and invalidate
|
ahansson
|
June 10th, 2015, 7:59 a.m.
|
|
|
|
[Submitted] mem: Spring cleaning of MSHR and MSHRQueue
|
ahansson
|
May 9th, 2013, 3:18 a.m.
|
|
|
|
[Submitted] mem: Squash prefetch requests from downstream caches
|
ahansson
|
April 23rd, 2014, 12:21 p.m.
|
|
|
|
[Submitted] mem: Store snoop filter lookup result to avoid second lookup
|
ahansson
|
August 21st, 2015, 3:49 p.m.
|
|
|
|
[Submitted] mem: Support any number of master-IDs in stride prefetcher
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
|
|
[Submitted] mem: support for gpu-style RMWs in ruby
|
atgutier
|
November 12th, 2015, 10:05 p.m.
|
|
|
|
[Submitted] mem: Support WriteInvalidate (again)
|
ahansson
|
November 25th, 2014, 9:49 a.m.
|
|
|
|
[Submitted] mem: Tidy up a few variables in the bus
|
ahansson
|
April 22nd, 2013, 3:32 p.m.
|
|
|
|
[Submitted] mem: Tidy up BaseCache parameters
|
ahansson
|
March 30th, 2015, 9:16 a.m.
|
|
|
|
[Submitted] mem: Tidy up bus addr range debug messages
|
ahansson
|
November 1st, 2012, 1:49 a.m.
|
|
|
|
[Submitted] Mem: Tidy up bus member variables types
|
ahansson
|
September 20th, 2012, 6:39 a.m.
|
|
|
|
[Submitted] mem: Tidy up CacheBlk class
|
ahansson
|
July 13th, 2015, 3:15 p.m.
|
|
|
|
[Submitted] mem: Tidy up packet
|
ahansson
|
July 13th, 2015, 3:15 p.m.
|
|
|
|
[Submitted] mem: Tidy up the bridge with const and additional checks
|
ahansson
|
June 4th, 2013, 10:49 a.m.
|
|
|
|
[Submitted] mem: Tie in the snoop filter in the coherent bus
|
ahansson
|
September 10th, 2014, 7:53 a.m.
|
|
|
|
[Submitted] mem: Tighten up cache constness and scoping
|
ahansson
|
February 14th, 2013, 1:53 a.m.
|
|
|
|
[Submitted] mem: Track DRAM read/write switching and add hysteresis
|
ahansson
|
March 17th, 2014, 8:16 a.m.
|
|
|
|
[Submitted] mem: Transition away from isSupplyExclusive for writebacks
|
ahansson
|
July 13th, 2015, 3:16 p.m.
|
|
|
|
[Discarded] MEM: TranslatingPorts are replaced with SETranslatingProxys
|
ahansson
|
November 28th, 2011, 10:16 a.m.
|
|
|
|
mem: Trigger DRAMCtrl resp queue panic
|
jthestness
|
February 2nd, 2016, 1:08 a.m.
|
|
|
|
[Submitted] MEM: Unify bus access methods and prepare for master/slave split
|
ahansson
|
February 29th, 2012, 3:06 a.m.
|
|
|
|
[Submitted] mem: Unify delayed packet deletion
|
ahansson
|
October 26th, 2015, 6:13 p.m.
|
|
|
|
[Submitted] mem: Unify request selection for read and write queues
|
ahansson
|
October 16th, 2013, 7:48 a.m.
|
|
|
|
[Submitted] mem: Update DDR3 and DDR4 based on datasheets
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
|
|
|
|
[Submitted] mem: update DDR3 die revision
|
cdunham
|
August 4th, 2016, 4:35 p.m.
|
|
|
|
[Submitted] mem: Update DRAM command scheduler for bank groups
|
ahansson
|
June 25th, 2015, 7:30 a.m.
|
|
|
|
[Submitted] mem: Update DRAM configuration names
|
cdunham
|
January 17th, 2017, 10:04 p.m.
|
|
|
|
[Submitted] mem: Update mostly exclusive cache policy to cover more cases
|
andysan
|
July 12th, 2016, 7:14 a.m.
|
|
|
|
[Discarded] mem: Update mostly exclusive cache policy to cover more cases
|
ahansson
|
April 11th, 2016, 5:08 p.m.
|
|
