Review Board 2.0.15


All Review Requests

Summary
Submitter
Posted Last Updated
python: added __nonzero__ function to SimObject Bool params
beckmann
April 4th, 2012, 9:59 p.m.
python: Adding event queue empty check after instantiation before startup
cdirik
December 4th, 2014, 6:45 p.m.
python: cleanup python code so stuff doesn't automatically happen at startup
nate
December 21st, 2010, 8:24 a.m.
python: Don't use Swig to cast stats
andysan
December 20th, 2016, 8:08 a.m.
python: figure out if the m5.internal package exists even with demandimport
nate
April 13th, 2011, 9:45 a.m.
python: get rid of internal.enums package.
stever
September 22nd, 2010, 8:44 a.m.
Python: Make the All proxy traverse SimObject children as well
ahansson
March 21st, 2012, 10:07 a.m.
python: Move native wrappers to the _m5 namespace
andysan
December 20th, 2016, 8:10 a.m.
python: Remove redundant drain when changing memory modes
andysan
June 8th, 2015, 11:32 a.m.
python: Rename doDrain()->drain() and make it do the right thing
ali
October 24th, 2012, 2:52 p.m.
[Discarded] python: Use PyBind11 instead of SWIG for Python wrappers
andysan
February 21st, 2017, 6:56 p.m.
range_map: Enable const find and iteration
ahansson
March 21st, 2012, 10:06 a.m.
rcs scripts: remove bbench.rcS
atgutier
March 22nd, 2013, 8:10 a.m.
refcnt: Update doxygen comments
nate
January 24th, 2011, 5:05 p.m.
RefCount: Add a unit test for reference counting pointers.
gblack
January 3rd, 2011, 12:42 p.m.
region: add a utility class for keeping track of regions of some range
nate
April 13th, 2011, 9:45 a.m.
regress: Regression tester updates
beckmann
August 5th, 2010, 9:22 p.m.
regression tester: add tests to exercise m5threads with the x86 ISA.
marc.orr
May 16th, 2012, 8:34 p.m.
regression tester: add tests to exercise m5threads with the x86 ISA.
marc.orr
May 20th, 2012, 6:38 p.m.
regression tester: Fix some bugs in simple-timing-mp-ruby.py.
marc.orr
May 16th, 2012, 6:09 p.m.
Regression: Add a test for x86 timing full system ruby simulation
nilay
December 30th, 2011, 4:27 p.m.
Regression: Add ANSI colours to highlight test status
ahansson
April 6th, 2012, 9:16 a.m.
Regression: Set the clock for twosys-tsunami CPUs
ahansson
September 21st, 2012, 9:54 a.m.
Regression: Update the regress script after SE/FS merge
ahansson
February 1st, 2012, 5:51 a.m.
Regression: Use addTwoLevelCacheHierarchy in configs
ahansson
September 27th, 2012, 6:28 a.m.
Regression: Use CPU clock and 32-byte width for L1-L2 bus
ahansson
September 27th, 2012, 6:30 a.m.
[Discarded] Regressions: Make the regression diffing script understand host_op_rate.
gblack
February 12th, 2012, 4:21 p.m.
Regressions: Make X86_FS run automatically, and move it's regressions to quick.
gblack
March 11th, 2011, 11:45 p.m.
Regressions: Start of new regression system
ali
August 30th, 2011, 10:38 a.m.
rename System.{hh,cc} to RubySystem.{hh,cc}
dhashe
July 13th, 2015, 7 p.m.
Reorder Cache Lookup in Protocol Files
nilay
January 25th, 2011, 9:18 a.m.
Replace curTick global variable with accessor functions.
stever
January 4th, 2011, 2:40 p.m.
Replace WARN and ERROR statements in Ruby
nilay
December 2nd, 2010, 1:14 p.m.
[Discarded] request: added split Paddr function
beckmann
April 4th, 2012, 9:58 p.m.
Require the SPARC FS image to be specified on the command line
jermar
June 13th, 2016, 8:27 a.m.
Reset and dump ruby stats along with gem5 stats
khaleghzadeh
May 18th, 2012, 6:21 a.m.
Reset/dump ruby stats when m5 stats are reset/dumped.
lluc.alvarez
September 20th, 2012, 8:29 a.m.
[Discarded] Resetting/dumping ruby_stats when gem5 stats is reset/dumped
khaleghzadeh
May 16th, 2012, 11:02 a.m.
[Discarded] Resetting/dumping ruby_stats when gem5 stats is reset/dumped
khaleghzadeh
May 16th, 2012, 10:30 p.m.
riscv: Fix crash when syscall argument reg index is too high
aroelke
January 12th, 2017, 9 p.m.
riscv: Remove ECALL tests from insttest
aroelke
January 12th, 2017, 9:18 p.m.
riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
aroelke
September 19th, 2016, 7:12 p.m.
riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD
aroelke
September 19th, 2016, 7:26 p.m.
riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A
aroelke
September 19th, 2016, 7:41 p.m.
riscv: [Patch 5/5] Added missing support for timing CPU models
aroelke
September 19th, 2016, 8:14 p.m.
riscv: [Patch 6/5] Improve Linux emulation for RISC-V
aroelke
October 14th, 2016, 6:17 p.m.
riscv: [Patch 7/5] Corrected LRSC semantics
aroelke
November 2nd, 2016, 7:34 p.m.
riscv: [Patch 8/5] Added some regression tests to RISC-V
aroelke
November 3rd, 2016, 7:36 p.m.
[Discarded] Root: Serialize the time sync state.
gblack
January 30th, 2011, 9:17 p.m.
ruby banked array: do away with event scheduling
nilay
September 13th, 2012, 7:58 a.m.
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