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[Submitted] sim: Reuse the same limit_event in simulate()
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cdunham
|
February 20th, 2015, 6:46 p.m.
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[Submitted] config: Add ability to exit simulation after initialization
|
cdunham
|
February 20th, 2015, 6:46 p.m.
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[Submitted] ext: Add SST connector
|
cdunham
|
February 20th, 2015, 6:47 p.m.
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[Submitted] config: Support full-system with SST's memory system
|
cdunham
|
February 20th, 2015, 6:47 p.m.
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[Discarded] config: Add --sst configuration option
|
cdunham
|
February 20th, 2015, 6:47 p.m.
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[Submitted] multi-gem5: add support for multi gem5 runs
|
cdunham
|
May 15th, 2015, 10:18 p.m.
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[Submitted] sim, arm: add checkpoint upgrader for d02b45a5
|
cdunham
|
May 27th, 2015, 10:18 p.m.
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[Submitted] multi-gem5: Add checkpoint support for multi gem5 runs
|
cdunham
|
June 1st, 2015, 8:05 p.m.
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[Submitted] scons: remove dead leading underscore check
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cdunham
|
June 8th, 2015, 11:35 p.m.
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[Submitted] sim: make warning for absent optional parameters optional
|
cdunham
|
June 30th, 2015, 12:35 a.m.
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[Submitted] sim: support checkpointing std::set<std::string>'s
|
cdunham
|
June 30th, 2015, 12:35 a.m.
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[Submitted] sim: tag-based checkpoint versioning
|
cdunham
|
June 30th, 2015, 12:35 a.m.
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[Submitted] arm: change instruction classes to catch hyp traps
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: invalidate TLB miscreg cache on modification of HSCTLR
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: enable EL2 support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: add stage2 translation support
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Add AArch64 hypervisor call instruction 'hvc'
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Fix EL perceived at TLB for address translation instructions
|
cdunham
|
June 21st, 2016, 1:41 p.m.
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[Submitted] arm: Add check to fault routing for hypervisor/virtualization
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Refactor aarch64 table walk logic to remove redundancy
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix stage 2 determination in table walker
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix secure state checking in various places
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix trapping to Hypervisor during MSR/MRS read/write
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Fix stage 2 memory attribute checking in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Add TLBI instruction for stage 2 IPA's
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: correctly assign faulting IPA's to HPFAR_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: Check TLB stage 2 permissions in AArch64
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: warn not fail on use of missing miscreg CNTHCTL_EL2
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] arm: refactor page table walking
|
cdunham
|
June 21st, 2016, 1:41 p.m.
|
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[Submitted] cpu: Change thread assignents for heterogenous SMT
|
cdunham
|
July 30th, 2015, 6:46 p.m.
|
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[Submitted] config,cpu: Add SMT support to Atomic and Timing CPUs
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
|
|
|
[Submitted] cpu: Add per-thread monitors
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
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|
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[Submitted] arm: tweak MPIDR setting when using SMT
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
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[Submitted] isa,cpu: Add support for FS SMT Interrupts
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
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|
[Submitted] cpu,isa,mem: Adds per-thread wakeup logic
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
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|
|
[Submitted] arm: Change TLB software caching
|
cdunham
|
July 30th, 2015, 6:47 p.m.
|
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[Submitted] probe: Add probe in Fetch, IEW, Rename and Commit
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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[Submitted] proto, probe: Add elastic trace probe to o3 cpu
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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[Submitted] mem: Add instruction sequence number to request
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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|
[Submitted] cpu: Add TraceCPU to playback elastic traces
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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|
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[Submitted] util: Add decode and encode scripts for elastic traces
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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|
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[Submitted] config: Enable elastic trace capture and replay in se/fs
|
cdunham
|
August 11th, 2015, 9:05 p.m.
|
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|
|
[Submitted] mem: Add initial HBM configurations
|
cdunham
|
August 12th, 2015, 5:38 p.m.
|
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|
[Submitted] isa: Add parameter to pick different decoder inside ISA
|
cdunham
|
August 12th, 2015, 5:38 p.m.
|
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|
[Submitted] base: remove Trace::enabled flag
|
cdunham
|
August 31st, 2015, 6:35 p.m.
|
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|
[Submitted] cpu: Create record type enum for elastic traces
|
cdunham
|
September 3rd, 2015, 4:17 p.m.
|
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|
[Submitted] cpu: Support virtual addr in elastic traces
|
cdunham
|
September 3rd, 2015, 4:17 p.m.
|
|
|
|
[Discarded] multi-gem5: Add an optional key parameter for the initparam pseudo instruction.
|
cdunham
|
September 21st, 2015, 6:59 p.m.
|
|
|
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[Discarded] multi-gem5: Add support for config scripts to run parallel gem5 simulations
|
cdunham
|
September 21st, 2015, 6:59 p.m.
|
|
|
|
[Discarded] multi-gem5: Fix draining and serialization
|
cdunham
|
September 21st, 2015, 6:59 p.m.
|
|
