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[Submitted] Mem: Put prefetcher notify call before packet is deleted.
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ali
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August 9th, 2011, 12:34 p.m.
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[Submitted] cpu: Initialize the O3 pipeline from startup()
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ali
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December 6th, 2012, 11:56 a.m.
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[Submitted] util: Add a script to convert gem5 stats to a Streamline .apc project
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ali
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September 27th, 2013, 12:23 a.m.
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[Submitted] simobject: Fix handling of parents for simobject vectors
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ali
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October 17th, 2013, 4:58 p.m.
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[Submitted] ARM: Decode neon memory instructions.
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ali
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August 13th, 2010, 9:48 a.m.
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[Submitted] Core: Add some documentation about the sim clocks.
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ali
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April 10th, 2011, 4:49 p.m.
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[Submitted] Debug: Add a function to cause the simulator to create a checkpoint from GDB.
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ali
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May 2nd, 2011, 3:22 p.m.
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[Submitted] O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
|
ali
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November 3rd, 2011, 1:24 p.m.
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[Submitted] prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
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ali
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January 26th, 2012, 4:25 a.m.
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[Submitted] ARM: Don't reset CPUs that are going to be switched in.
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ali
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March 6th, 2012, 4:17 p.m.
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[Submitted] base: split out the VncServer into a VncInput and Server classes
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ali
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October 24th, 2012, 2:19 p.m.
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[Submitted] mem: Remove the IIC replacement policy
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ali
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November 2nd, 2012, 10:10 a.m.
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[Submitted] config: Move CPU handover logic to m5.switchCpus()
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ali
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January 7th, 2013, 11:24 a.m.
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[Submitted] kvm: Basic support for hardware virtualized CPUs
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ali
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March 8th, 2013, 6:13 a.m.
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[Submitted] ARM: Implement CLREX
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ali
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August 13th, 2010, 9:53 a.m.
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[Submitted] ARM: Implement all ARM SIMD instructions.
|
ali
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August 23rd, 2010, 9:29 a.m.
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[Submitted] CPU/Cache: Fix some errors exposed by valgrind
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ali
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September 22nd, 2010, 1:43 a.m.
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[Submitted] ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
|
ali
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November 8th, 2010, 3:28 p.m.
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[Submitted] O3: Support timing translations for O3 CPU fetch.
|
ali
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December 6th, 2010, 3:46 p.m.
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[Submitted] ARM: Reset m5 stats when program resets performance counters.
|
ali
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February 11th, 2011, 4:34 p.m.
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[Submitted] O3: Send instruction back to fetch on squash to seed predecoder correctly.
|
ali
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February 25th, 2011, 8:58 p.m.
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[Submitted] ARM: Identify branches as conditional or unconditional and direct or indirect.
|
ali
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March 11th, 2011, 3:19 p.m.
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[Submitted] mem: fix cache stats to use request ids correctly
|
ali
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February 4th, 2012, 12:24 p.m.
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[Submitted] base: Check for static_assert support and provide fallback
|
ali
|
September 7th, 2012, 12:23 p.m.
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[Submitted] python: Rename doDrain()->drain() and make it do the right thing
|
ali
|
October 24th, 2012, 2:52 p.m.
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[Submitted] cpu: rename the misleading inSyscall to noSquashFromTC
|
ali
|
December 6th, 2012, 11:45 a.m.
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[Submitted] arm: Enable support for triggering a sim panic on kernel panics
|
ali
|
February 13th, 2013, 8:48 a.m.
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[Submitted] cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
|
ali
|
November 30th, 2013, 11:49 p.m.
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[Submitted] ARM: Add system for ARM/Linux and bootstrapping
|
ali
|
August 13th, 2010, 9:40 a.m.
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[Discarded] ARM: make predicated-false instruction to move data from a old register.
|
ali
|
August 13th, 2010, 10:03 a.m.
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[Submitted] ARM: Seperate the queues of L1 and L2 walker states.
|
ali
|
August 23rd, 2010, 9:32 a.m.
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[Submitted] ARM: Fix SRS instruction to micro-code memory operation and register update.
|
ali
|
November 11th, 2010, 4:12 p.m.
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[Submitted] o3: Fix front-end pipeline interlock behavior
|
ali
|
June 12th, 2014, 10:49 p.m.
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[Submitted] O3: Fix itstate prediction and recovery.
|
ali
|
January 12th, 2011, 9:09 a.m.
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[Submitted] ARM: Implement L2CTLR num cpus register.
|
ali
|
July 13th, 2011, 8:57 a.m.
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[Submitted] gem5ops: Implement Java JNI for gem5Ops
|
ali
|
August 19th, 2011, 3:19 p.m.
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[Submitted] O3: Add stat that counts how many cycles the O3 cpu was quiesced.
|
ali
|
November 3rd, 2011, 1:23 p.m.
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[Submitted] ARM: Add support for running multiple systems
|
ali
|
December 16th, 2011, 1:31 p.m.
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[Submitted] stats: Provide a mechanism to get a callback when stats are dumped.
|
ali
|
February 13th, 2012, 3:41 p.m.
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[Submitted] cpu: Make sure that a drained timing CPU isn't executing ucode
|
ali
|
December 6th, 2012, 12:16 p.m.
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[Submitted] O3: Handle loads when the destination is the PC.
|
ali
|
August 13th, 2010, 9:51 a.m.
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[Submitted] ARM: Implement functional virtual to physical address translation
|
ali
|
September 16th, 2010, 12:47 a.m.
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[Submitted] O3: Support squashing all state after special instruction
|
ali
|
November 19th, 2010, 4:06 p.m.
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[Submitted] ARM: Construct the predicate test register for more instruction programatically.
|
ali
|
May 4th, 2011, 6:44 p.m.
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[Submitted] ARM: Add support for Versatile Express extended memory map
|
ali
|
February 22nd, 2012, 12:03 p.m.
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[Submitted] Cache: Panic if you attempt to create a checkpoint with a cache in the system
|
ali
|
May 2nd, 2012, 1:07 p.m.
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[Submitted] sim: Include object header files in SWIG interfaces
|
ali
|
October 24th, 2012, 2:26 p.m.
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[Submitted] ARM: Finish the timing translation when taking a fault.
|
ali
|
August 13th, 2010, 9:39 a.m.
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[Submitted] ARM: Don't write tracedata in completeAcc as we might hav freed it already
|
ali
|
August 13th, 2010, 9:58 a.m.
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[Submitted] ARM: Use less micro-ops for register update loads if possible.
|
ali
|
August 23rd, 2010, 9:30 a.m.
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