Review Board 2.0.15


Review requests for Default

Summary Submitter
Posted Last Updated
sim: SystemC hosting
ahansson
September 29th, 2014, 10:45 a.m.
mem: Clean up packet data allocation
ahansson
November 17th, 2014, 6:17 a.m.
arm: Fix TLB ignoring faults when table walking
ahansson
November 25th, 2014, 9:48 a.m.
mem: Add MemChecker and MemCheckerMonitor
ahansson
December 12th, 2014, 5:45 p.m.
MEM: Explicit ports and Python binding on CopyEngine
ahansson
January 18th, 2012, 2:34 a.m.
MEM: Fix master/slave ports in Ruby and non-regression scripts
ahansson
February 13th, 2012, 11:05 a.m.
cpu: Move invldPid constant from Request to BaseCPU
ahansson
August 13th, 2015, 8:29 p.m.
[Discarded] mem: Modernise the CacheSet class, and avoid templates
ahansson
August 31st, 2015, 9:20 a.m.
Port: Separate the port and the interface protocol
ahansson
July 10th, 2012, 4:07 a.m.
Device: Remove overloaded pio_latency parameter
ahansson
August 3rd, 2012, 9:05 a.m.
clang: Fix issues identified by the clang static analyzer
ahansson
September 11th, 2012, 3:41 a.m.
Regression: Use CPU clock and 32-byte width for L1-L2 bus
ahansson
September 27th, 2012, 6:30 a.m.
base: Encapsulate the underlying fields in AddrRange
ahansson
October 30th, 2012, 8:57 a.m.
stats: Implement code to manipulate vector2d stats in python
ahansson
January 15th, 2013, 10:25 a.m.
mem: Enforce strict use of busFirst- and busLastWordTime
ahansson
February 14th, 2013, 1:53 a.m.
config: Make configs/common a Python package
ahansson
October 13th, 2016, 2:10 p.m.
util: Auto generate the packet proto definitions
ahansson
April 22nd, 2013, 2:44 p.m.
cpu: Fix a bug in the O3 CPU introduced by the cache line patch
ahansson
August 7th, 2013, 3:12 p.m.
sim: Clarify the difference between tracing and debugging
ahansson
October 17th, 2013, 5:37 p.m.
stats: Method stats source
ahansson
April 23rd, 2014, 12:21 p.m.
arm: Make memory ops work on 64bit/128-bit quantities
ahansson
August 13th, 2014, 2:08 p.m.
cpu: use probes infrastructure to do simpoint profiling
ahansson
September 10th, 2014, 7:51 a.m.
arm: Add helper methods to setup architected PMU events
ahansson
September 29th, 2014, 10:39 a.m.
mem: Change prefetcher to use random_mt
ahansson
December 12th, 2014, 5:50 p.m.
cpu: Ensure timing CPU sinks response before sending new request
ahansson
January 27th, 2015, 10:19 a.m.
mem: Fix prefetchSquash + memInhibitAsserted bug
ahansson
February 13th, 2015, 8:36 a.m.
mem, cpu: Add a separate flag for strictly ordered memory
ahansson
March 30th, 2015, 9:17 a.m.
MEM: Remove Port removeConn and MemObject deletePortRefs
ahansson
December 19th, 2011, 5:57 a.m.
Ruby: Change the access permissions for MOESI hammer
ahansson
January 10th, 2012, 9:18 a.m.
mem: Add snoops for CleanEvicts and Writebacks in atomic mode
ahansson
August 19th, 2015, 9:07 a.m.
gcc: Enable Link-Time Optimization for gcc >= 4.6
ahansson
May 2nd, 2012, 11:24 a.m.
Config: Exit with fatal if a port is already connected
ahansson
May 18th, 2012, 9:10 a.m.
mem: Unify delayed packet deletion
ahansson
October 26th, 2015, 6:13 p.m.
Bridge: Remove NACKs in the bridge and unify with packet queue
ahansson
July 21st, 2012, 5:09 a.m.
AddrRange: Simplify Range by removing stream input/output
ahansson
September 3rd, 2012, 9:21 p.m.
mem: Remove the joining of neighbouring ranges
ahansson
December 6th, 2012, 8:01 p.m.
scons: Allow pkg-config to fail and continue
ahansson
January 8th, 2013, 6:47 a.m.
mem: Merge interleaved ranges when creating backing store
ahansson
February 19th, 2013, 6:38 a.m.
[Discarded] config: Change default memory size to 256 MB
ahansson
July 5th, 2013, 1:18 p.m.
[Discarded] dev: Split Ethernet into EtherDevice and leave controllers (1/2)
ahansson
August 19th, 2013, 9:39 a.m.
mem: Less conservative tRAS in DRAM configurations
ahansson
October 16th, 2013, 7:43 a.m.
cpu: Add flag name printing to StaticInst
ahansson
April 23rd, 2014, 12:25 p.m.
config: Refactor RealviewEMM to fit into new config system
ahansson
August 20th, 2014, 8:34 a.m.
mem: Add DDR4 bank group timing
ahansson
September 10th, 2014, 7:52 a.m.
mem: Add missig timing and current parameters to DRAM configs
ahansson
September 29th, 2014, 10:42 a.m.
mem: Remove redundant Packet::allocate calls
ahansson
November 17th, 2014, 6:14 a.m.
mem: Remove unused RequestState in the bridge
ahansson
January 5th, 2015, 4:53 p.m.
base: Do not dereference NULL in CompoundFlag creation
ahansson
February 5th, 2015, 11:36 a.m.
base: Allow multiple interleaved ranges
ahansson
May 8th, 2015, 1:10 p.m.
mem: Add ReadCleanReq and ReadSharedReq packets
ahansson
June 10th, 2015, 7:59 a.m.
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