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[Submitted] dev: Set HDLCD default pixel clock for 1080p @ 60Hz
|
ahansson
|
April 23rd, 2014, 12:18 p.m.
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[Submitted] mem: Add DRAM cycle time
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
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[Submitted] arm: Fix v8 neon latency issue for loads/stores
|
ahansson
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August 13th, 2014, 2:07 p.m.
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[Submitted] cpu: Remove unused deallocateContext calls
|
ahansson
|
September 11th, 2014, 2:01 p.m.
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[Submitted] arm: Add a model of an ARM PMUv3
|
ahansson
|
September 29th, 2014, 10:38 a.m.
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[Submitted] mem: Rework the structuring of the prefetchers
|
ahansson
|
December 12th, 2014, 5:47 p.m.
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[Submitted] style: Update the style checker to handle new include order
|
ahansson
|
January 26th, 2015, 5:55 p.m.
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[Submitted] arm: Add a GICv2m device
|
ahansson
|
March 6th, 2015, 1:39 p.m.
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[Submitted] mem: Pass shared downstream through caches
|
ahansson
|
March 30th, 2015, 9:17 a.m.
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[Submitted] MEM: Add port proxies instead of non-structural ports
|
ahansson
|
December 19th, 2011, 5:53 a.m.
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[Submitted] MEM: Differentiate functional cache accesses from CPU and memory
|
ahansson
|
January 5th, 2012, 5:17 a.m.
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[Submitted] Ruby: Connect system port in Ruby network test
|
ahansson
|
January 27th, 2012, 3:57 a.m.
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|
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[Submitted] mem: Do not include snoop-filter latency in crossbar occupancy
|
ahansson
|
August 19th, 2015, 9:06 a.m.
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[Submitted] swig: Use SWIG from environment when determining version
|
ahansson
|
June 20th, 2012, 4:32 p.m.
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[Submitted] base: Add wrapped protobuf input stream
|
ahansson
|
December 6th, 2012, 7:53 p.m.
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|
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stats: Store vector stats using doubles and compress with zlib
|
ahansson
|
January 15th, 2013, 10:34 a.m.
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[Submitted] mem: Fix SenderState related cache deadlock
|
ahansson
|
February 14th, 2013, 6:13 a.m.
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|
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[Submitted] cpu: Use request flags in trace playback
|
ahansson
|
March 28th, 2013, 3:28 a.m.
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[Submitted] cpu: Move traffic generator sending out of generator states
|
ahansson
|
April 23rd, 2013, 12:26 a.m.
|
|
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[Submitted] config: Add a system clock command-line option
|
ahansson
|
May 24th, 2013, 3:28 a.m.
|
|
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[Submitted] power: Add voltage domains to the clock domains
|
ahansson
|
June 27th, 2013, 4:40 p.m.
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|
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|
[Submitted] util: Add ini string as tooltip info in dot output
|
ahansson
|
August 19th, 2013, 9:33 a.m.
|
|
|
|
[Submitted] mem: Fix DRAM bank occupancy for streaming access
|
ahansson
|
October 16th, 2013, 7:39 a.m.
|
|
|
|
[Submitted] mem: Add a wrapped DRAMSim2 memory controller
|
ahansson
|
November 14th, 2013, 6:24 p.m.
|
|
|
|
[Submitted] ruby: Move Ruby debug flags to ruby dir and remove stale options
|
ahansson
|
March 16th, 2014, 12:55 p.m.
|
|
|
|
[Submitted] arm: add preliminary ISA splits for ARM arch
|
ahansson
|
April 23rd, 2014, 12:24 p.m.
|
|
|
|
[Submitted] mem: Add bank and rank indices as fields to the DRAM bank
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
|
|
|
|
[Submitted] config: Add SubSystem container for simobjects
|
ahansson
|
July 28th, 2014, 5:50 a.m.
|
|
|
|
[Submitted] misc: README direct to website for dependencies
|
ahansson
|
August 17th, 2014, 10:46 a.m.
|
|
|
|
[Submitted] dev: Add a VirtIO block device model
|
ahansson
|
September 10th, 2014, 7:52 a.m.
|
|
|
|
[Submitted] arch: Use shared_ptr for all Faults
|
ahansson
|
September 29th, 2014, 10:40 a.m.
|
|
|
|
[Submitted] mem: Add a GDDR5 DRAM config
|
ahansson
|
November 17th, 2014, 6:13 a.m.
|
|
|
|
[Submitted] mem: Clean up Request initialisation
|
ahansson
|
January 5th, 2015, 4:35 p.m.
|
|
|
|
[Submitted] sim: Move the BaseTLB to src/arch/generic/
|
ahansson
|
February 5th, 2015, 10:59 a.m.
|
|
|
|
[Submitted] mem: Add option to force in-order insertion in PacketQueue
|
ahansson
|
February 19th, 2015, 7:56 a.m.
|
|
|
|
[Submitted] mem: Remove redundant allocateUncachedReadBuffer in cache
|
ahansson
|
March 17th, 2015, 7:09 p.m.
|
|
|
|
[Submitted] Ruby: Remove the physMemPort and instead access memory directly
|
ahansson
|
March 20th, 2012, 8:31 a.m.
|
|
|
|
[Submitted] Bus: Turn the PortId into a transport function parameter
|
ahansson
|
May 23rd, 2012, 6:34 a.m.
|
|
|
|
[Submitted] mem: Add PacketInfo to be used for packet probe points
|
ahansson
|
September 25th, 2015, 2:29 p.m.
|
|
|
|
[Submitted] Port: Make getAddrRanges const
|
ahansson
|
June 6th, 2012, 9:45 a.m.
|
|
|
|
[Submitted] mem: Be less conservative in clearing load locks in the cache
|
ahansson
|
January 21st, 2016, 6:12 p.m.
|
|
|
|
[Submitted] dev: Make default clock more reasonable for system and devices
|
ahansson
|
October 23rd, 2012, 2:28 a.m.
|
|
|
|
[Submitted] mem: Add DDR3 and LPDDR2 DRAM controller configurations
|
ahansson
|
December 6th, 2012, 8:31 p.m.
|
|
|
|
[Submitted] alpha: Remove ALPHA tru64 support and associated tests
|
ahansson
|
October 27th, 2016, 7:45 a.m.
|
|
|
|
[Submitted] mem: Adding verbose debug output in the memory system
|
ahansson
|
March 14th, 2013, 7:05 a.m.
|
|
|
|
[Submitted] mem: Align cache timing to clock edges
|
ahansson
|
June 4th, 2013, 10:46 a.m.
|
|
|
|
[Submitted] mem: Use STL deque in favour of list for DRAM queues
|
ahansson
|
July 18th, 2013, 12:59 p.m.
|
|
|
|
[Submitted] mem: Fix bug in PhysicalMemory use of mmap and munmap
|
ahansson
|
February 13th, 2014, 2:41 p.m.
|
|
|
|
[Submitted] mem: Limit the accesses to a page before forcing a precharge
|
ahansson
|
March 7th, 2014, 11:40 p.m.
|
|
|
|
[Submitted] ext: disable PLY debugging
|
ahansson
|
April 23rd, 2014, 12:11 p.m.
|
|
