|
|
[Submitted] x86: add LongModeAddressSize function to cpuid
|
majiuyue
|
June 13th, 2014, 9:14 a.m.
|
|
|
|
[Submitted] cpu: Fix SMT scheduling issue with the O3 cpu
|
ali
|
June 12th, 2014, 10:50 p.m.
|
|
|
|
[Submitted] cpu: Fix incorrect speculative branch predictor behavior
|
ali
|
June 12th, 2014, 10:50 p.m.
|
|
|
|
[Submitted] cpu: Add a fetch queue to the o3 cpu.
|
ali
|
June 12th, 2014, 10:49 p.m.
|
|
|
|
[Submitted] o3: Fix front-end pipeline interlock behavior
|
ali
|
June 12th, 2014, 10:49 p.m.
|
|
|
|
[Submitted] cpu: Change writeback modeling for outstanding instructions
|
ali
|
June 12th, 2014, 10:48 p.m.
|
|
|
|
[Submitted] arch: Properly guess OpClass from optional StaticInst flags
|
ali
|
June 12th, 2014, 10:47 p.m.
|
|
|
|
[Submitted] config: Change parsing of Addr so hex values work from scripts
|
ali
|
June 12th, 2014, 10:47 p.m.
|
|
|
|
[Submitted] mem: Properly set cache block status fields on writebacks
|
ali
|
June 12th, 2014, 10:47 p.m.
|
|
|
|
[Submitted] cache: Fix handling of LL/SC requests under contention
|
ali
|
June 12th, 2014, 10:46 p.m.
|
|
|
|
[Submitted] power: Add basic DVFS support for gem5
|
ahansson
|
June 11th, 2014, 5:03 p.m.
|
|
|
|
[Submitted] sim: More rigorous clocking comments
|
jthestness
|
June 7th, 2014, 10:02 p.m.
|
|
|
|
[Submitted] Util: Do not style check symlinks
|
jthestness
|
June 7th, 2014, 10 p.m.
|
|
|
|
[Submitted] mem: DRAMPower trace formatting script
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
|
|
|
[Submitted] mem: DRAMPower trace output
|
ahansson
|
June 3rd, 2014, 4:34 p.m.
|
|
|
|
[Submitted] mem: Add bank and rank indices as fields to the DRAM bank
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
|
|
|
|
[Submitted] scons: Bump the compiler version to gcc 4.6 and clang 3.0
|
ahansson
|
June 3rd, 2014, 4:33 p.m.
|
|
|
|
[Submitted] style: eliminate equality tests with true and false
|
stever
|
June 1st, 2014, 12:47 a.m.
|
|
|
|
[Submitted] cpu: `Minor' in-order CPU model
|
ali
|
May 30th, 2014, 3:23 p.m.
|
|
|
|
[Submitted] config: remove unecessary assignment of etherlink interfaces
|
atgutier
|
May 15th, 2014, 4:03 p.m.
|
|
|
|
o3: issue excl. prefetch as soon as store address is available
|
stever
|
May 14th, 2014, 5:47 a.m.
|
|
|
|
[Discarded] ruby: don't make O3 CPU squash on loads that hit outstanding requests
|
stever
|
May 14th, 2014, 5:47 a.m.
|
|
|
|
[Submitted] o3: make LSQ full check more selective
|
stever
|
May 14th, 2014, 5:46 a.m.
|
|
|
|
[Submitted] o3: split load & store queue full cases
|
stever
|
May 14th, 2014, 5:46 a.m.
|
|
|
|
cache: enable multiple stores per cycle
|
stever
|
May 14th, 2014, 5:46 a.m.
|
|
|
|
[Submitted] x86: fix table walker assertion
|
stever
|
May 14th, 2014, 5:46 a.m.
|
|
|
|
[Submitted] tests: Reflect name change in DRAM tests
|
ahansson
|
April 23rd, 2014, 12:38 p.m.
|
|
|
|
[Submitted] mem: Update DDR3 and DDR4 based on datasheets
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
|
|
|
|
[Submitted] mem: Add DRAM cycle time
|
ahansson
|
April 23rd, 2014, 12:37 p.m.
|
|
|
|
[Submitted] mem: Simplify DRAM response scheduling
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] mem: Add precharge all (PREA) to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] mem: Remove printing of DRAM params
|
ahansson
|
April 23rd, 2014, 12:36 p.m.
|
|
|
|
[Submitted] mem: Add tRTP to the DRAM controller
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Merge DRAM latency calculation and bank state update
|
ahansson
|
April 23rd, 2014, 12:35 p.m.
|
|
|
|
[Submitted] mem: Add tWR to DRAM activate and precharge constraints
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Merge DRAM page-management calculations
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Add DRAM power states to the controller
|
ahansson
|
April 23rd, 2014, 12:34 p.m.
|
|
|
|
[Submitted] mem: Ensure DRAM refresh respects timings
|
ahansson
|
April 23rd, 2014, 12:33 p.m.
|
|
|
|
[Submitted] mem: Make DRAM read/write switching less conservative
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
|
|
|
|
[Submitted] arm: Make sure UndefinedInstructions are properly initialized
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
|
|
|
|
[Submitted] arm: allow DC instructions by default so SE mode works
|
ahansson
|
April 23rd, 2014, 12:27 p.m.
|
|
|
|
[Submitted] sim, arm: implement more of the at variety syscalls
|
ahansson
|
April 23rd, 2014, 12:26 p.m.
|
|
|
|
[Submitted] cpu: Useful getters for ActivityRecorder
|
ahansson
|
April 23rd, 2014, 12:26 p.m.
|
|
|
|
[Submitted] cpu: Add flag name printing to StaticInst
|
ahansson
|
April 23rd, 2014, 12:25 p.m.
|
|
|
|
[Submitted] cpu: Timebuf const accessors
|
ahansson
|
April 23rd, 2014, 12:25 p.m.
|
|
|
|
[Submitted] arm: Add branch flags onto macroops
|
ahansson
|
April 23rd, 2014, 12:25 p.m.
|
|
|
|
[Submitted] cpu: Allow setWhen on trace objects
|
ahansson
|
April 23rd, 2014, 12:24 p.m.
|
|
|
|
[Submitted] arm: add preliminary ISA splits for ARM arch
|
ahansson
|
April 23rd, 2014, 12:24 p.m.
|
|
|
|
[Discarded] arch: support dynamic ISA file generation in per-ISA SConscripts
|
ahansson
|
April 23rd, 2014, 12:23 p.m.
|
|
|
|
[Discarded] arch: support dynamic ISA file generation in SConscripts
|
ahansson
|
April 23rd, 2014, 12:23 p.m.
|
|
