|
|
[Submitted] ARM: DPRINTFs prints disassembly for uops
|
ali
|
August 13th, 2010, 10:04 a.m.
|
|
|
|
[Submitted] ARM: Support unaligned memory access. Without this flag set,
|
ali
|
August 23rd, 2010, 9:32 a.m.
|
|
|
|
[Submitted] imported patch ext/noisa.patch
|
ali
|
November 11th, 2010, 1:08 p.m.
|
|
|
|
[Submitted] arch: Properly guess OpClass from optional StaticInst flags
|
ali
|
June 12th, 2014, 10:47 p.m.
|
|
|
|
[Submitted] The ARM decoder should not panic when decoding undefined holes in the
|
ali
|
December 6th, 2010, 3:57 p.m.
|
|
|
|
[Submitted] O3: Fix pipeline restart when a table walk completes in the fetch stage.
|
ali
|
January 27th, 2011, 6:24 p.m.
|
|
|
|
[Submitted] WorkItems: Enables run time sampling for code marked using pseudo insts.
|
ali
|
December 16th, 2011, 1:31 p.m.
|
|
|
|
[Discarded] IGbE: Add additional features required by igb kernel driver in 2.6.28+.
|
ali
|
February 13th, 2012, 3:41 p.m.
|
|
|
|
[Submitted] cpu: Make sure that a drained timing CPU isn't executing ucode
|
ali
|
December 6th, 2012, 12:16 p.m.
|
|
|
|
[Submitted] arm: Add a method to query interrupt state ignoring CPSR masks
|
ali
|
March 8th, 2013, 6:21 a.m.
|
|
|
|
[Submitted] sim: separate nextCycle() and nearestClockEdge() in clockedObjects
|
ali
|
March 26th, 2013, 1:51 p.m.
|
|
|
|
[Submitted] ARM: mark msr/mrs instructions as SerializeBefore/After
|
ali
|
August 13th, 2010, 9:51 a.m.
|
|
|
|
[Submitted] ARM: Implement a CLCD Frame buffer
|
ali
|
September 16th, 2010, 12:47 a.m.
|
|
|
|
[Submitted] O3: Support squashing all state after special instruction
|
ali
|
November 19th, 2010, 4:06 p.m.
|
|
|
|
[Submitted] ARM: Construct the predicate test register for more instruction programatically.
|
ali
|
May 4th, 2011, 6:44 p.m.
|
|
|
|
[Submitted] Config: Add support for a Self.all proxy object
|
ali
|
May 26th, 2011, 7:15 p.m.
|
|
|
|
[Submitted] ARM: Add support for Versatile Express extended memory map
|
ali
|
February 22nd, 2012, 12:03 p.m.
|
|
|
|
[Submitted] ARM: Update m5op assembly for thumb compilation.
|
ali
|
May 2nd, 2012, 1:07 p.m.
|
|
|
|
[Submitted] build: Add missing dependencies when building param SWIG interfaces
|
ali
|
September 7th, 2012, 12:20 p.m.
|
|
|
|
[Submitted] pci: Make Python wrapper cast to the right type
|
ali
|
October 24th, 2012, 2:23 p.m.
|
|
|
|
[Submitted] Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled.
|
ali
|
August 13th, 2010, 9:39 a.m.
|
|
|
|
[Submitted] ARM: Make sure that software prefetch instructions can't change the state of the TLB
|
ali
|
August 13th, 2010, 9:59 a.m.
|
|
|
|
[Submitted] ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing
|
ali
|
August 23rd, 2010, 9:31 a.m.
|
|
|
|
[Submitted] ARM: Keep the warnings to a minimum.
|
ali
|
October 2nd, 2010, 7:12 p.m.
|
|
|
|
[Submitted] O3: Make all instructions that write a misc register not perform the write until commit.
|
ali
|
November 8th, 2010, 3:39 p.m.
|
|
|
|
[Submitted] O3: Fix bug when a squash occurs right before TLB miss returns.
|
ali
|
February 11th, 2011, 4:38 p.m.
|
|
|
|
[Submitted] O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
|
ali
|
May 16th, 2011, 2:35 p.m.
|
|
|
|
[Submitted] ARM: Mark some variables uncacheable until boot all CPUs are enabled.
|
ali
|
August 9th, 2011, 12:36 p.m.
|
|
|
|
[Submitted] cpu: Unify SimpleCPU and O3 CPU serialization code
|
ali
|
December 6th, 2012, 11:58 a.m.
|
|
|
|
[Submitted] cpu: Construct ROB with cpu params struct instead of each variable
|
ali
|
October 17th, 2013, 4:58 p.m.
|
|
|
|
[Submitted] ARM: Exclusive accessse must be double word aligned
|
ali
|
August 13th, 2010, 9:49 a.m.
|
|
|
|
[Submitted] O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
|
ali
|
November 3rd, 2011, 1:24 p.m.
|
|
|
|
[Submitted] prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
|
ali
|
January 26th, 2012, 4:25 a.m.
|
|
|
|
[Submitted] sim: Remove FastAlloc
|
ali
|
May 30th, 2012, 10:30 a.m.
|
|
|
|
[Submitted] base: split out the VncServer into a VncInput and Server classes
|
ali
|
October 24th, 2012, 2:19 p.m.
|
|
|
|
[Submitted] sim, arch: Add support for invalidating TLBs when draining
|
ali
|
November 2nd, 2012, 10:11 a.m.
|
|
|
|
[Submitted] config: Remove O3 dependencies
|
ali
|
January 7th, 2013, 11:25 a.m.
|
|
|
|
[Submitted] ARM: Implement DSB, DMB, ISB
|
ali
|
August 13th, 2010, 9:55 a.m.
|
|
|
|
[Submitted] ARM: Fix type comparison warnings in Neon
|
ali
|
August 23rd, 2010, 9:29 a.m.
|
|
|
|
[Submitted] ARM: Add support for a dumb IDE controller
|
ali
|
November 8th, 2010, 3:29 p.m.
|
|
|
|
[Submitted] ARM: Fix rfe macroops.
|
ali
|
February 11th, 2011, 4:32 p.m.
|
|
|
|
[Submitted] O3: Cleanup the commitInfo comm struct.
|
ali
|
February 25th, 2011, 8:58 p.m.
|
|
|
|
[Submitted] ARM: Allow conditional quiesce instructions.
|
ali
|
March 11th, 2011, 3:15 p.m.
|
|
|
|
[Submitted] ARM: Tag appropriate instructions as IsReturn
|
ali
|
March 30th, 2011, 8:55 a.m.
|
|
|
|
[Submitted] cpu: remove legion tracer
|
ali
|
December 10th, 2014, 5:54 p.m.
|
|
|
|
[Submitted] Util: Added script to semantically diff two config.ini files
|
ali
|
September 7th, 2012, 12:24 p.m.
|
|
|
|
[Submitted] python: Rename doDrain()->drain() and make it do the right thing
|
ali
|
October 24th, 2012, 2:52 p.m.
|
|
|
|
[Submitted] cpu: rename the misleading inSyscall to noSquashFromTC
|
ali
|
December 6th, 2012, 11:45 a.m.
|
|
|
|
[Submitted] cpu: fix case with o3 cpu blocking and unblocking decode in cycle
|
ali
|
January 22nd, 2013, 1:47 p.m.
|
|
|
|
[Submitted] cpu: generate SimPoint basic block vector profiles
|
ali
|
February 13th, 2013, 8:47 a.m.
|
|
